Electricity: electrical systems and devices – Safety and protection of systems and devices
Reexamination Certificate
2000-03-17
2002-07-16
Tso, Edward H. (Department: 2838)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Reexamination Certificate
active
06421213
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to electronic circuitry, and more specifically to a chip that can detect a tamper voltage and prevent that voltage from corrupting the other circuitry on the chip.
BACKGROUND OF THE INVENTION
Electrical signals are typically routed to and from a semiconductor chip or integrated circuit through bond pads. These bond pads are typically formed of aluminum pads that are electrically connected to the external pins on the chip's package by thin gold bond wires.
Most of the bond pads on a chip are typically used during the normal operation of the chip by the end user. However, a manufacturer may include “test pads” that may be used by it to facilitate testing of the chip. For example, and referring to
FIG. 1
, some flash EPROM (erasable-programmable-read-only-memory) chips contain a “Vpp” test pad
2
whereby a voltage (i.e., Vpp) can be directly routed to a Flash EPROM memory array
4
in order to perform certain tests. The Vpp voltage is typically a relatively high voltage which is generated internally on the chip by a Vpp generator
6
, as shown in FIG.
1
. As one of skill in the art of Flash EPROM design will recognize, Vpp generator
6
is typically a “charge pump” circuit which is capable of boosting Vpp to a voltage higher than the normal voltage levels used elsewhere on the chip. The high Vpp voltage (typically 12 Volts) is used by the Flash EPROM during the programming (i.e., writing) and erase operations. However, because the magnitude of Vpp generated by Vpp generator
6
can be difficult to control, or because it may be desirable to bypass the internal generation of Vpp, it is sometimes desirable during testing to externally route Vpp into the memory array
4
from Vpp test pad
2
. The manufacturer of the chip can then use Vpp test pad
2
to provide a wider range of signals to memory array
4
, with such signals being particularly useful in assessing the quality and reliability of the chip before sale to a prospective purchaser.
It is typical for the manufacturer to disconnect (i.e., open circuit) a test pad after testing has finished and before the chip is sent to the purchaser or end user, for example, at location
8
in FIG.
1
. In a Flash EPROM chip this disconnection of the Vpp test bond pad is necessary to ensure that the customer or other end user does not tamper with the Vpp voltage and disturb the data state of the memory array. For example, it is important to disconnect the Vpp test pad in Flash EPROM chips that are used in solid state debit cards so that the user will be unable to disturb the data within the cards in a manner which would reflect a higher credit balance than the user actually has.
Test bond pads have been disconnected in the prior art in at least three ways. First, a trace which carries signals to and from the test pad can be ablated by using a laser or a particle beam. Typically, the laser or particle beam is directed to a target area on the trace with sufficient energy to remove the trace in that location. Second, the test pad can be made to incorporate a fuse or antifuse which, when exposed to high current or voltage, will create a short circuit or open circuit respectively. Depending on the location of the fuse or antifuse with respect to the test pad, the test pad can be electrically disconnected from the circuitry on the chip. However, these prior art techniques for disconnecting a test pad suffer from several drawbacks. Both the ablation/fusing techniques may not result in a perfect open circuit and instead may leave some amount of residual conductive material between the test pad and the circuitry. The resulting resistive path may, in the case of a Flash EPROM, allow the user to tamper with the Vpp voltage and thus corrupt data. Also, these prior art techniques, being destructive in nature, may cause other unwanted damage to the chip. Moreover, the creation of a target area or the fuse/antifuse may involve the use of extra processing or testing steps during the manufacture of the chip, adding extra cost and complexity.
A third way of disconnecting a test bond pad from other circuitry on a chip is to use a transistor as a switch to controllably allow signals to pass to and from the test bond pad. If the test bond pad is to be used during a special test mode, a signal will be sent to the gate of the transistor to turn it on and thereby connect the test pad to the rest of the circuitry under test. While the use of a transistor avoids the disadvantages associated with ablation or fusing, it is susceptible to tampering by the application of voltages at the test pad that are beyond the normal operating limits of the transistor. For example, an usually high voltage may damage the transistor, allowing it to be bypassed. Also, an usually low voltage, and perhaps even a negative voltage, could cause the transistor to conduct despite the lack of a gate signal, again bypassing the transistor. In either circumstance, the result, in a Flash EPROM, could be the possible corruption of data due to intentional tampering.
Given these drawbacks of the prior art, it would be desirable to effectively disconnect a test pad such as the Vpp test pad of a Flash EPROM in such a manner to prevent a tamper condition from corrupting the data within the chip.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a system is disclosed for isolating a bond pad from the rest of the circuitry of a semiconductor chip in a manner that protects the chip from applied signals that are outside the normal operating range and which tamper with the operation of the system. The system includes the use of a controllable switch for routing the signal from the bond pad to the circuit and a detector for detecting a tamper condition on the bond pad. The detection of a tamper condition causes the detector to inform the microcontroller on the chip to, for example, terminate the operation in progress, perform a controlled system shutdown, disable pre-arranged functions, or record the fact that a tamper condition occurred.
REFERENCES:
patent: 5309387 (1994-05-01), Mori
patent: 5345225 (1994-09-01), Davis
patent: 5956408 (1999-09-01), Arnold
patent: 6127745 (2000-10-01), Bolz
Advanced Technology & Materials Inc.
Chappuis Margaret
Hultquist Steven J.
Tibbits Pia
Tso Edward H.
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