Method and apparatus for designing an emulation chip using a...

Details Method and apparatus for designing an emulation chip using a... Method and apparatus for designing an emulation chip using a...

2006-11-22

2010-06-15

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S023000, C703S025000, C703S027000, C714S037000, C326S038000

Reexamination Certificate

active

07739094

ABSTRACT:
A method and apparatus for designing a processor-based emulation integrated circuit (chip) having a selectable fastpath topology. Included are initially designing an N-level fastpath topology comprising a plurality of processors, then reducing the N-level fastpath topology to an M-level topology such that the performance of the topology meets a design criterion, e.g., capable of evaluating data during a time of an emulation step. In this manner, an emulator chip designer may configure the fastpath topologies without redesigning the chip layout.

REFERENCES:
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 2003/0083776 (2003-05-01), Schauer et al.
patent: 2003/0212539 (2003-11-01), Beausoleil et al.

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