Boots – shoes – and leggings
Patent
1996-10-17
1998-11-24
Beausoliel, Jr., Robert W.
Boots, shoes, and leggings
364578, 3642323, G06F 11263
Patent
active
058419675
ABSTRACT:
A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.
REFERENCES:
patent: 3106698 (1963-10-01), Unger
patent: 3287702 (1966-11-01), Borck, Jr. et al.
patent: 3287703 (1966-11-01), Slotnick
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3928730 (1975-12-01), Agaard et al.
patent: 4020469 (1977-04-01), Manning
patent: 4032899 (1977-06-01), Jenny et al.
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4315315 (1982-02-01), Kossiakoff
patent: 4357678 (1982-11-01), Davis
patent: 4386403 (1983-05-01), Hsieh et al.
patent: 4404635 (1983-09-01), Flaker
patent: 4459694 (1984-07-01), Ueno et al.
patent: 4488354 (1984-12-01), Chan et al.
patent: 4503386 (1985-03-01), DasGupta et al.
patent: 4510602 (1985-04-01), Engdahl et al.
patent: 4524240 (1985-06-01), Stock et al.
patent: 4525789 (1985-07-01), Kemper et al.
patent: 4527115 (1985-07-01), Mehrotra et al.
patent: 4539564 (1985-09-01), Smithson
patent: 4541071 (1985-09-01), Ohmori
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4578761 (1986-03-01), Gray
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4600846 (1986-07-01), Burrows
patent: 4612618 (1986-09-01), Pryor et al.
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4642487 (1987-02-01), Carter
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4656592 (1987-04-01), Spaanenburg et al.
patent: 4674089 (1987-06-01), Poret et al.
patent: 4675832 (1987-06-01), Robinson et al.
patent: 4695740 (1987-09-01), Carter
patent: 4695950 (1987-09-01), Brandt et al.
patent: 4695999 (1987-09-01), Lebizay
patent: 4697241 (1987-09-01), Lavi
patent: 4700187 (1987-10-01), Furtek
patent: 4706216 (1987-11-01), Carter
patent: 4713557 (1987-12-01), Carter
patent: 4722084 (1988-01-01), Morton
patent: 4725835 (1988-02-01), Schreiner et al.
patent: 4736338 (1988-04-01), Saxe et al.
patent: 4740919 (1988-04-01), Elmer
patent: 4744084 (1988-05-01), Beck et al.
patent: 4747102 (1988-05-01), Funatsu
patent: 4752887 (1988-06-01), Kuwahara
patent: 4758745 (1988-07-01), Er Gamal et al.
patent: 4758985 (1988-07-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4768196 (1988-08-01), Jou et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4782440 (1988-11-01), Nomizu et al.
patent: 4786904 (1988-11-01), Graham et al.
patent: 4787061 (1988-11-01), Nei et al.
patent: 4787062 (1988-11-01), Nei et al.
patent: 4791602 (1988-12-01), Resnick
patent: 4803636 (1989-02-01), Nishiyama et al.
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 4815003 (1989-03-01), Patatunda et al.
patent: 4823276 (1989-04-01), Hiwatashi
patent: 4827427 (1989-05-01), Hyduke
patent: 4829202 (1989-05-01), Austin
patent: 4835705 (1989-05-01), Fujino et al.
patent: 4845633 (1989-07-01), Furtek
patent: 4849904 (1989-07-01), Aipperspach et al.
patent: 4849928 (1989-07-01), Hauck
patent: 4854039 (1989-08-01), Wendt
patent: 4855669 (1989-08-01), Mahoney
patent: 4862347 (1989-08-01), Rudy
patent: 4864165 (1989-09-01), Hoberman et al.
patent: 4868419 (1989-09-01), Austin
patent: 4870302 (1989-09-01), Freeman
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 4876466 (1989-10-01), Kondou et al.
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 4901259 (1990-02-01), Watkins
patent: 4901260 (1990-02-01), Lubachevsky
patent: 4908772 (1990-03-01), Chi
patent: 4914612 (1990-04-01), Beece et al.
patent: 4918440 (1990-04-01), Furtek
patent: 4918594 (1990-04-01), Onizuka
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4924429 (1990-05-01), Kurashita et al.
patent: 4931946 (1990-06-01), Ravindra et al.
patent: 4935734 (1990-06-01), Austin
patent: 4937827 (1990-06-01), Beck et al.
patent: 4942536 (1990-07-01), Watanabe et al.
patent: 4942615 (1990-07-01), Hirose
patent: 4945503 (1990-07-01), Takasaki
patent: 4949275 (1990-08-01), Nonaka
patent: 4951220 (1990-08-01), Ramacher et al.
patent: 4958324 (1990-09-01), Devin
patent: 4965739 (1990-10-01), Ng
patent: 4972372 (1990-11-01), Ueno
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5023775 (1991-06-01), Poret
patent: 5036473 (1991-07-01), Butts et al.
patent: 5041986 (1991-08-01), Tanishita
patent: 5046017 (1991-09-01), Yuyama et al.
patent: 5051938 (1991-09-01), Hyduke
patent: 5053980 (1991-10-01), Kanazawa
patent: 5081602 (1992-01-01), Glover
patent: 5083083 (1992-01-01), El-Ayat et al.
patent: 5084824 (1992-01-01), Lam et al.
patent: 5093920 (1992-03-01), Agrawal et al.
patent: 5109353 (1992-04-01), Sample et al.
patent: 5126966 (1992-06-01), Hafeman et al.
patent: 5128871 (1992-07-01), Schmitz
patent: 5140526 (1992-08-01), McDermith et al.
patent: 5172011 (1992-12-01), Leuthold et la.
patent: 5224055 (1993-06-01), Grundy et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5231588 (1993-07-01), Agrawal et al.
patent: 5231589 (1993-07-01), Itoh et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5253363 (1993-10-01), Hyman
patent: 5259006 (1993-11-01), Price et al.
patent: 5280826 (1994-01-01), Kondo et al.
patent: 5329470 (1994-07-01), Sample et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5339262 (1994-08-01), Rostoker et al.
patent: 5352123 (1994-10-01), Sample et al.
patent: 5386550 (1995-01-01), Yumioka et al.
patent: 5425036 (1995-06-01), Lui et al.
patent: 5437037 (1995-07-01), Furuichi
patent: 5448496 (1995-09-01), Butts et al.
patent: 5448522 (1995-09-01), Huang
patent: 5452231 (1995-09-01), Butts et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5475830 (1995-12-01), Chen
patent: 5477475 (1995-12-01), Sample et al.
patent: 5535223 (1996-07-01), Horstmann et al.
patent: 5544069 (1996-08-01), Mohsen
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 5563829 (1996-10-01), Huang
patent: 5572710 (1996-11-01), Asano et al.
patent: 5574388 (1996-11-01), Barbier et al.
patent: 5581738 (1996-12-01), Dombrowski
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5604888 (1997-02-01), Kiani-Shabestori et al.
patent: 5612891 (1997-03-01), Butts et al.
patent: 5633813 (1997-05-01), Srinivasan
patent: 5649176 (1997-07-01), Selvidge et al.
patent: 5659716 (1997-08-01), Selvidge et al.
patent: 5699283 (1997-12-01), Okazaki et al.
Hou, et al., "A High Level Synthesis Tool for Systolic Designs," IEEE, 1988, pp. 665-673.
"Gate Station Reference Manual," Mentor Graphics Corp., 1987 (excerpts).
Dussault, et al., "A High Level Synthesis Tool for MOS Chip Design," 21st Design Automation conference, 1984, IEEE, pp. 308-314.
DeMicheli, et al., "Hercules--A System for High Level Synthesis," 25th ACM/IEEE Design Automation Conference, 1988, pp. 483-488.
J.Babb, A.Agarwal "More Virtual Wires", article from webmaster@cag.lcs.mit.edu Feb. 3, 1995.
R.Tessier "More Virtual Pictures", article from webmaster@cag.lcs.mit.edu Feb. 3, 1995.
Varghese et al., "An Efficient Logic Emulation System", IEEE Publication, pp. 171-174, 1993.
Brown et al., "Issues in the Design of a Logic Simulator: Element Modelling for Efficiency", IEEE Publication, pp. 21-27, Feb. 1996.
Agrawal, "Mixed Behavior-Logic Simulation in a Hardware Accelerator", IEEE Pub., pp. 9.2.1-9.2.4, 1990.
"The Homogenous Computational Medium; New Technology For Computation", Concurrent Logic Inc., Jan. 26, 1987.
Spandorfer, "Synthesis of Logic Functions on an Array of Integrated Circuits", Contract Report AFCRI-6-6-298, Oct. 31, 1965.
J.Babb, R.Tessier, A.Agarwal, V
Bershteyn Mikhail
Sample Stephen P.
Baderman Scott T.
Beausoliel, Jr. Robert W.
Quickturn Design Systems Inc.
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