Method and apparatus for dependency checking in a multi-pipeline

Details Method and apparatus for dependency checking in a multi-pipeline Method and apparatus for dependency checking in a multi-pipeline

1994-10-03

1995-05-16

Lall, Parshuiam S.

Boots, shoes, and leggings

395800, 364230, 3642302, 3642624, 364263, G06F 940

Patent

active

054169135

ABSTRACT:
In a superscalar processor capable of executing two integer instructions in parallel, an array of comparators is provided to check for all combinations of register dependency between a pair of sequential program instructions. Additional logic is provided to validate the register fields of the instructions. If no impermissible dependencies are detected and all register fields are valid, the instructions are issued and executed in parallel. Otherwise, the instructions are executed sequentially.

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