Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-03-01
2002-10-15
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S123000, C438S106000, C438S121000, C257S666000, C257S673000, C257S692000, C257S734000
Reexamination Certificate
active
06465278
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to semiconductor devices and more particularly to an apparatus and method for delivering electrical power to the bond pads of a semiconductor die.
BACKGROUND OF THE INVENTION
An important consideration in the packaging of integrated circuits is the efficient delivery of power and ground feeds to the semiconductor die of the integrated circuit. One method for the delivery of power to the integrated circuit involves lead frame over chip (LOC) packaging, in which a metal lead frame rests on top of the semiconductor die. The metal lead frames employed in LOC packaging often include two metal power buses, one power bus at a positive voltage potential and the other at a ground voltage potential. Each bus or metal lead runs lengthwise along the top of the semiconductor die. The power buses provide a means by which the bond wires can be easily coupled between the power buses and the bond pads, which bond pads often lie in the center top surface of the semiconductor die. In a typical configuration, there may be half a dozen or more connections made between the bond pads of the semiconductor die and the power buses.
One drawback of LOC packaging for delivering power to the die is the capacitive effects created by the combination of the metal lead frame and the semiconductor die. In the configuration described, both the semiconductor die and the metal lead frame behave as capacitor plates, producing capacitive effects on the signals being output from the semiconductor die. The signals being transferred to and from the semiconductor die often have to switch between potential levels, and the capacitive effects produced by the combination of the semiconductor die and the lead frame tend to inhibit the fast switching between voltage potentials because of the damping effects experienced during the transition between voltage levels.
To compensate for capacitive effects created by the combination of the semiconductor die and the metal lead frame, integrated circuit designers have designed chips in which the signals that are most sensitive to parasitic capacitance, such as high frequency output signals in memory chips, and the bond pads for these signals have been moved to the four corners of the semiconductor die. In this manner, the output signals leaving the semiconductor die from the four corners of the chip are between the metal lead frame and the semiconductor die—the two plates producing capacitive effects—for only a very short distance, thereby reducing the capacitive loading on the signals that are most sensitive to parasitic capacitance. An additional benefit of placing the output signals on the four corners of the semiconductor die is a reduction in the distance that the signal must travel on the bond wires and on the lead frame before reaching the outside of the integrated circuit packaging.
If bond pads and output signals are placed on the outside corners of the semiconductor die, however, dedicated output drivers ordinarily must be placed adjacent the bond pads to drive the output signals. These output drivers, however, often require massive and dedicated power and ground feeds.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus for delivering power to a semiconductor die is provided that substantially eliminates or reduces problems associated with previously developed power delivery methods..
The method and apparatus involve a lead frame that is coupled to the surface of a semiconductor die. A series of bond pads are formed on the surface of the semiconductor die in each of the corners of the semiconductor die. The metal frame includes first and second voltage leads. These leads are formed to have two corner portions and two arm portions so that each of the voltage leads is adjacent to the series of bond pads in each of the four corners of the semiconductor die.
A technical advantage of the present invention is that both voltage leads of the metal frame are adjacent to each series of bond pads formed on the semiconductor die, including the bond pads on the outer edges of the semiconductor die, allowing the signals from the bond pads on the outer edges of the semiconductor die to be closest physically to the signal leads of the lead frame and the exterior of the integrated circuit packaging.
Another technical advantage of the present invention is that the first and second voltage leads are physically adjacent one another, thereby introducing capacitive effects that aid the stability of the voltage potentials delivered by the first and second voltage leads.
Still another technical advantage of the present invention is that power is delivered to the bond pads of the semiconductor die substantially along the length of the voltage leads, which have greater electrical conductivity as compared to the bond wires coupling the bond pads to the voltage leads.
Another technical advantage of the present invention is the provision of a metal frame that allows voltages to be delivered to the corners as well as the center of a semiconductor die in a manner that removes the need to have power circuitry included in the integrated circuitry of the semiconductor die.
Additional technical advantages should be readily apparent from the drawings, description, and claims.
REFERENCES:
patent: 5455200 (1995-10-01), Bigler et al.
patent: 5648680 (1997-07-01), Ogawa et al.
patent: 5907186 (1999-05-01), Kang et al.
patent: 5945728 (1999-08-01), Dobkin et al.
patent: 5977614 (1999-11-01), Takeuchi
patent: 6114627 (2000-09-01), Moden
Bowers Charles
Brady III Wade James
Geyer Scott B
Holland Robby T.
Telecky , Jr. Frederick J.
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