Method and apparatus for delaying a load miss flush until...

Details Method and apparatus for delaying a load miss flush until... Method and apparatus for delaying a load miss flush until...

2011-05-31

2011-05-31

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reexamination Certificate

active

07953960

ABSTRACT:
A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.

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