Coded data generation or conversion – Converter compensation
Reexamination Certificate
1999-05-05
2001-10-16
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S144000
Reexamination Certificate
active
06304199
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to digital to analog converters. More particularly, the invention relates to a digital to analog converter output stages.
BACKGROUND OF THE INVENTION
The functional operation of a digital to analog converter (DAC) is well known. Generally, a DAC accepts an digital input signal and converts it into an analog output signal. The digital input signal has a range of digital codes which are converted into a continuous range of analog signal levels of the analog output signal. DACs are useful to interface digital systems to analog systems. Applications of DACs include video or graphic display drivers, audio systems, digital signal processing systems, function generators, digital attenuators, precision instruments and data acquisition systems including automated test equipment.
There are a variety of DACs available for converting digital input signals into analog output signals depending upon the desired conversion functionality. The variations in the DACs available may have different predetermined resolutions of a digital input signal, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Additionally there are a number of DAC performance factors to consider such as settling time, full scale transition time, accuracy or linearity, and a factor previously mentioned, resolution.
The digital input signal is a number of bits wide which defines the resolution, the number of output levels or quantization levels and the total number of digital codes that are acceptable. If the digital input signal is m-bits wide, there are 2
m
output levels and 2
m−1
steps between levels. The range of analog output signal values usually depend upon an analog reference. The analog reference may be internally generated but is usually externally provided for precision. The analog output signal range may be proportional to the digital input signal over a fixed analog reference level as in a fixed reference DAC. Alternatively, the analog output signal may be the product of a varying input analog reference level and the digital code of the digital input signal as in multiplying DACs. The analog output signal may be unipolar ranging in either positive values or negative values or it may be bipolar ranging between both positive and negative output values. The analog output signal may be an analog voltage signal or an analog current signal.
Additionally, the type of electronic circuitry used to form a DAC varies as well. Bipolar junction transistor (BJT) technology, metal oxide semiconductor (MOS) technology or a combination thereof are used to construct DACs. BJT technology may be PNP technology with PNP transistors or NPN with NPN transistors or both, while MOS technology may be PMOS with P-channel field effect transistors (PFET), NMOS with N-channel field effect transistors (PFET) or CMOS technology having both PFETs and NFETs.
Referring now to
FIG. 1A
, a block diagram of a DAC
100
has a digital input signal DIN
101
, a positive analog supply voltage level AVref+
104
, and a negative analog supply voltage level AVref−
105
in order to generate an analog voltage output signal on the DAC output terminal AVOUT
110
. Alternatively DAC
100
can generate an analog current output signal with minor changes to its circuit configuration. For simplicity in discussion, consider DAC
100
to be a fixed reference DAC such that the output voltage range of AVOUT
110
is a function of DIN
101
and the range of voltage is defined by the predetermined voltage levels of AVref+
104
and AVref−
105
. DIN
101
is m bit wide. The predetermined value of m is the resolution of the DAC. The selected circuitry for DAC
100
varies depending upon a number of factors including power supply range and desired parameters of input and output signals. As illustrated in
FIG. 1B
, DAC
100
includes a signal converter
112
coupled to an amplifier or buffer
114
. Some forms of DACs, specifically current output DACs, may not include the buffer
114
and require external amplification. Signal converter
112
converts DIN
101
into a form of analog signal on the intermediate signal line VLADR
120
which is input to buffer
114
. Buffer
114
buffers the analog signal generated by the signal converter
112
from a load that may be coupled to the DAC output terminal AVOUT
110
. The signal converter
112
includes a switched R-2R ladder
116
and a switch controller
118
. Switch controller
118
controls switches within the switched R-2R ladder
116
to cause it to convert the value of DIN
101
into an analog signal.
Referring now to
FIG. 2A
, a prior art switched R-2R ladder
116
is illustrated. The switched R-2R ladder
116
is a 4 bit inverted R-2R ladder to provide an analog voltage output signal but may be easily expanded to m-bits with the addition of other intermediate R-2R switch legs and additional switch control lines. Alternatively, a non-inverted R-2R ladder could be used to provide an analog current output signal. Signals DBn/DBp
201
are selectively controlled by the switch controller
118
in order to generate an analog voltage output signal VLADR
120
. DBn/DBp
201
switches ON and OFF NFETS
211
-
214
and PFETS
216
-
219
in order to change the voltage division of the R-2R resistor network between AVref+
104
and AVref−
105
and VLADR
120
. Inverters
246
-
249
generate the inverter polarity of the switch control lines D
4
Bp-D
1
Bp
241
-
244
to control the NFETs
236
-
239
to form fully complementary switches with PFETs
216
-
219
. NFET
211
and PFET
216
/NFET
236
represent the MSB of the DAC and can couple 8/16 of the reference voltage range to VLADR
120
. NFET
212
and PFET
217
/NFET
237
can couple 4/16 of the reference voltage range to VLADR
120
. NFET
213
and PFET
218
/NFET
238
can couple 2/16 of the reference voltage range to VLADR
120
. NFET
214
and PFET
219
/NFET
239
represent the LSB of the DAC and can couple 1/16 of the reference voltage range to VLADR
120
. Thus, when the digital code is 1111, PFETs
216
-
219
and NFETs
236
-
239
are all ON and NFETS
211
-
214
are all OFF such that 15/16 of the reference voltage range is coupled to VLADR
120
. When the digital code is 0000, NFETS
211
-
214
are all ON and PFETs
216
-
219
and NFETs
236
-
239
are all OFF such that no current flows between AVref+
104
and AVref−
105
in a resistor and AVref−
105
is coupled to VLADR
120
.
The circuit connections of the switched R-2R ladder
116
are now described. NFET
215
has its gate tied to terminal leg gate voltage signal, TLGV
235
, such that it is constantly turned ON. The voltage level of TLGV
235
is the same as the turn ON voltage level for all the NFETs
211
-
214
switching AVref−in the switched R-2R ladder
116
. NFETS
211
-
215
have sources connected to AVref−
105
and drains respectively connected to first ends of resistors
220
-
223
. PFETS
216
-
219
have sources connected to AVref+
104
and drains respectively connected to first ends of resistors
220
-
224
. NFETs
236
-
239
have sources respectively connected to the first ends of resistors
220
-
223
and drains connected to AVref+
104
. The gates of NFETS
211
-
214
are respectively connected to signals D
4
Bn-D
1
Bn
231
-
234
and gates of PFETS
216
-
219
are respectively connected to signals D
4
Bp-D
1
Bp
241
-
244
of DBn/DBp
201
. The inverters
246
-
249
have inputs respectively coupled to signals D
4
Bp-D
1
Bp
241
-
244
to generate the inverted polarity for coupling their outputs to the gates of NFETs
236
-
239
respectively. Signals D
4
Bn-D
1
Bn
231
-
234
and signals D
4
Bp-D
1
Bp
241
-
244
are collectively referred to as signals DBn/DBp
201
from switch controller
118
. Resistors
220
-
223
each have a resistance value of 2R. Resistors
224
-
228
each having a resistance value of R are coupled in series together with a first end of resistor
228
cou
Castaneda David
Fang Gary G.
Rahim Chowdhury F.
Blakely , Sokoloff, Taylor & Zafman LLP
Jean-Pierre Peguy
Maxim Integrated Products Inc.
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