Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-12-03
2004-10-05
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S763010
Reexamination Certificate
active
06801049
ABSTRACT:
This is a NATIONAL STAGE application of PCT/JP01/02910 filed on Apr. 4, 2001, further of a Japanese patent application, 2000-101867 filed on Apr. 4, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for fault analysis of semiconductor integrated circuit, and the present application is related to the Japanese patent application described as below. For designated states which permit incorporation of a document by reference, contents of the application specified as below is incorporated in the present application by reference, thereby contents of the application specified as below becomes a part of the present application.
Japanese Patent Application No. 2000-101867
Application date: Heisei 12, April 4
2. Description of the Related Art
A conventional method for fault analysis of semiconductor integrated circuit (IC) utilized an electron beam tester, an emission microscope, or a liquid crystal to specify the fault location of the semiconductor IC. The fault analysis of semiconductor IC using an electron beam tester is a method to specify the fault location, such as logic fault, by obtaining a voltage difference between a normal circuit and a defect circuit. The voltage difference can be obtained while observing, using an electron beam tester, a voltage contrast image of the tested IC to which an input test pattern is given. This is disclosed, for example, in Japanese Patent Publication No. 45423/93. The fault analysis of semiconductor IC using an emission microscope is a method to specify the current leak position by matching the emission image of the tested IC's wiring pattern with the light image from current leak detected by the photon detector (emission microscope), which can detect extremely dim light of a photon level. It is reported, for example, in Japanese Patent Publication No. 4128/98. The fault analysis of semiconductor IC using a liquid crystal is a method to specify the fault location, such as current leak accompanied with some heat, by observing the optical change of liquid crystal, spread on the surface of the tested IC, elicited by the input test pattern. It is reported, for example, in Japanese Patent Publication No. 74911/93.
On the other hand, fault analysis using fault simulation is a nondestructive fault analysis method. The fault simulation simulates the output from the output terminal responding to the given input test pattern after assuming a fault inside the IC. The results of the simulation are arranged by matching the input-output logic value with the correspondingly assumed fault, so called, fault dictionary. The fault analysis by the fault simulation is, when the output signal from the output terminal is different from the expected value responding to the input test pattern to the tested IC, performed by matching the input-output logic values from the tested IC with the fault dictionary.
In order to work on faults without a logical error such as a short defect or a current leak defect, a fault analysis method based on IDDQ fault information of semiconductor IC and the input test pattern, accompanied by IDDQ (quiescent power supply current) test and the fault simulation, is proposed. The fault analysis method accompanied by IDDQ test is disclosed, for example, in the Japanese Patent Publication No. 201486/96.
However, the fault analysis methods using the electron beam tester, the emission microscope, and the liquid crystal are costly since these methods require the semiconductor IC to be opened and the chip surface exposed Moreover, multi-layer wiring and large integration of semiconductor IC's render it difficult to specify fault locations.
A fault analysis method with input output signal response and fault simulation can simulate only a fault of which model is stuck on single signal line (
0
or
1
), so called single-stuck-at fault (stuck-at-
0
or stuck-at-
1
), but neither a fault stuck on multiple signal line, delay fault, nor fault of short circuit in signal wires. Also, since this fault analysis method can not spe cify the fault location if the discrepancy between the output value of IC and the expected value is not detected, it cannot guess the fault location of non-logical faults, for example short circuit, where the logic did not become abnormal even with a fault inside the circuit. Furthermore, although fault locations of a delay fault and/or open defect accompanying delay fault can be specified with programming the fault model for the delay fault in the fault simulation, it is difficult to generate a test pattern for observing effects of the delay fault in the semiconductor IC and to effectively specify the fault location of the delay fault.
Furthermore, in the fault analysis accompanied by the IDDQ testing and fault simulation, since the IDDQ testing is a method designed to measure a power supply current of semiconductor IC in its stable state and does not have the transient information of the semiconductor IC, it is difficult to specify the fault location altering a delay time of a circuit. Also, because the IDDQ testing, since it is primarily applied to a short defect, cannot detect open defect and abnormality (parametric defects) of local process parameter (sheet resistance, oxidation etc.) causing delay faults, it has been a problem that it could not detect the fault location of delay fault, open defect, and parametric defect.
Therefore, a fault analysis method is needed that can effectively detect a delay fault and/or open defect and presume the fault location.
The object of the present invention is to provide a method and apparatus which can specify the fault location of a delay fault and/or open defect in a semiconductor IC without processing the semiconductor IC devices.
SUMMARY OF THE INVENTION
In order to achieve the above and other objects, according to the first aspect of the present invention, a fault analysis method for presuming a fault location of a semiconductor IC comprising the steps of: applying a power supply voltage to the semiconductor IC; supplying a test pattern sequence having a plurality of test patterns to the semiconductor IC; storing an analysis point included in the IC, the electric potential of which changes in accordance with change of the supplied test pattern, to be corresponding to the test pattern sequence; measuring a transient power supply current generated on the semiconductor IC in accordance with the change of the test pattern and determining whether the transient current shows abnormality or not; and presuming a fault location out of the analysis points based on the test pattern sequence, where the transient power supply current shows abnormality, and the analysis point stored to be corresponding to the test pattern sequence.
Moreover, it is preferable that the transient power supply current is determined to be abnormal when pulse width of the transient power supply current is over a predetermined value in the step of determining.
Moreover, the transient power supply current may be determined to be abnormal when instant value of the transient power supply current at a predetermined time point is over a predetermined value in the step of determining.
Moreover, the transient power supply current may be determined to be abnormal in case time integral of the transient power supply current is over a predetermined value in the step of determining.
Moreover, it is preferable that the method further comprises a step of producing the predetermined value by simulation.
Moreover, it is preferable that the step of presuming a fault location presumes the analysis point, which is placed to be corresponding to all of the test pattern sequence where the transient power supply current shows abnormality, to be the fault location in case the transient power supply current shows abnormality for two or more of the plurality of test pattern sequence.
It is preferable that the step of presuming comprises the steps of: deleting, in case the transient power supply current shows abnormal
Hashimoto Yoshihiro
Ishida Masahiro
Yamaguchi Takahiro
Advantest Corporation
Nguyen Tung X.
Pert Evan
Rosenthal & Osha L.L.P.
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