Patent
1996-07-08
1997-07-29
Harrell, Robert B.
395567, 395800, G09G 302
Patent
active
056527748
ABSTRACT:
A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.
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Eickemeyer Richard James
Malik Nadeem
Saha Avijit
Ward Charles Gorham
Harrell Robert B.
Henkler Richard A.
International Business Machines - Corporation
Najjar Saleh
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