Method and apparatus for decreasing layout area in a...

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C341S162000

Reexamination Certificate

active

07471227

ABSTRACT:
In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter.

REFERENCES:
patent: 5771012 (1998-06-01), Shu et al.
patent: 7002507 (2006-02-01), Kobayashi et al.
patent: 7250895 (2007-07-01), Kurose et al.
patent: 7324036 (2008-01-01), Petre et al.
patent: 2005/0156775 (2005-07-01), Petre et al.
U.S. Appl. No. 11/211,566, filed Aug. 26, 2005, Cho et al.
Dallas Semiconductor Maxim, Mar. 1, 2001, found at http://www.maxim-ic.com/an1023.
B. Vaz, N. Paulino, J. Goes R. Costa, R. Tavares, A. Steiger-Garcao, Design of Low-Voltage CMOS Pipelined ADC's using 1 pico-Joule of Energy per Conversion, IEEE 2002.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for decreasing layout area in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for decreasing layout area in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for decreasing layout area in a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4024822

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.