Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2006-08-18
2008-12-30
Williams, Howard (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S162000
Reexamination Certificate
active
07471227
ABSTRACT:
In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter.
REFERENCES:
patent: 5771012 (1998-06-01), Shu et al.
patent: 7002507 (2006-02-01), Kobayashi et al.
patent: 7250895 (2007-07-01), Kurose et al.
patent: 7324036 (2008-01-01), Petre et al.
patent: 2005/0156775 (2005-07-01), Petre et al.
U.S. Appl. No. 11/211,566, filed Aug. 26, 2005, Cho et al.
Dallas Semiconductor Maxim, Mar. 1, 2001, found at http://www.maxim-ic.com/an1023.
B. Vaz, N. Paulino, J. Goes R. Costa, R. Tavares, A. Steiger-Garcao, Design of Low-Voltage CMOS Pipelined ADC's using 1 pico-Joule of Energy per Conversion, IEEE 2002.
Fletcher Yoder
Lauture Joseph
Micro)n Technology, Inc.
Williams Howard
LandOfFree
Method and apparatus for decreasing layout area in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for decreasing layout area in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for decreasing layout area in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4024822