Patent
1997-08-06
1998-08-18
Lall, Parshotam S.
395380, 395388, 395391, G06F 930
Patent
active
057969736
ABSTRACT:
A superscalar complex instruction set computer ("CISC") processor having a reduced instruction set ("RISC") superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes "predecode" information, a byte queue (BYTEQ) which is a queue of aligned instruction and predecode information of the "predicted executed" state, and an instruction decoder (IDECODE) which generates type, opcode, and operand pointer values for RISC-like operation based on the aligned predecoded x86 instructions in the BYTEQ and determines the number of possible x86 instruction dispatch for shifting the BYTEQ. The IDECODE includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer directs x86 instructions from the BYTEQ to the conversion paths. A select circuit (ROPSELECTx) assembles ROP information from the appropriate conversion paths. A share circuit processes ROP information from the ROPSELECTx for shared resources. ROP type and opcode information is dispatched from the IDECODE to the RISC core. Pointers to the A and B source operands are furnished by the IDECODE to a register file and to a reorder buffer in the RISC core which in turn furnish the appropriate "predicted executed" versions of the A and B operands to various functional units in the RISC core in coordination with the ROP type and opcode information.
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Goddard Michael D.
Witt David B.
Advanced Micro Devices , Inc.
Lall Parshotam S.
O'Brien David W.
Vu Viet
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