Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2000-07-26
2002-06-04
Diep, Nhon T (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C348S400100, C382S232000
Reexamination Certificate
active
06400765
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to video decoders and more particularly to decoding of compressed video.
BACKGROUND OF THE INVENTION
Processing of video data is known to include receiving a stream of video data and rendering it such that it may be presented on a display device. The video stream includes a plurality of video frames and/or fields. Typically, video frames are generated for display on a composite display devices, such as CRT monitors, High Definition Televisions, and/or LCD panels, while video fields are typically displayed on interlaced devices such as television sets. For each video frame, or video field, the video data includes information regarding the object-elements (e.g., triangles) that make up the image(s) being rendered. For example, the information may be vertex data of the triangles that includes physical coordinates, texture coordinates, color information/or alpha-blending information and/or other information needed to render the triangles.
In a computer system, a video graphics processor is operably coupled to receive an uncompressed stream of video data from a central processing unit and/or a video input device, such as a television decoder. Upon receiving the stream of video data, the video graphics processor produces pixel data therefrom and provides the pixel data to the display device. The video graphics processor produces the pixel data by interpreting the object-element parameters, generating pixel data for each pixel of an object-element, and storing the pixel data in a frame buffer until a full frame of data is stored. Such processing is usually done in accordance with the refresh rate of the display, which is typically 50 hertz, 60 hertz, 75 hertz, 90 hertz, etc.
A video graphics processor may also process compressed video data that has been compressed in accordance with the Motion Picture Expert Group (MPEG) 2 standard. In general, the MPEG 2 standard compresses a video frame by encoding the difference between a current video frame and reference video frames. As is known, MPEG 2 provides three types of video frames, an I frame, a P frame, and a B frame. The I frame is an independent frame and is compressed independent of other frames. The P frame is compressed based on differences between it and a reference I frame. The B frame is compressed based on the differences between it, a reference P frame and a reference I frame.
The MPEG 2 standard also prescribes an architecture for an MPEG 2 video decoder. Such a decoder includes a variable length decoding section, inverse scan section, inverse quantization, inverse discreet cosine transform section, motion compensation section, and memory. The implementation of the architecture prescribed by the MPEG 2 standard is costly, in part, due to the cost of the inverse discreet cosine transform function. Such a function requires several separate memory sections to properly process the inverse discrete cosine transform function. Such additional memory requires substantial die area, which increase the cost of implementing the decoder on an integrated circuit.
Therefore, a need exists for a method and apparatus that more efficiently processes the video decoding of compressed video there by reducing the memory requirements.
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Chow Paul
Porter Allen J.
Strasser David A.
ATI Technologies Inc.
Diep Nhon T
Vedder Price Kaufman & Kammholz
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