Method and apparatus for debugging, verifying and validating...

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C717S152000, C717S152000

Reexamination Certificate

active

06173440

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computers and, more particularly, to computer software debugging, verifying and validating devices and techniques.
2. Description of Related Art
The process of correcting developmental errors within computer software code is commonly referred to as debugging. A typical debugging procedure entails a software designer executing the prototype software and attempting to determine which portions of the code are responsible for incorrect operation. The software developer typically examines a failure within the software code and attempts to determine the portion, module or line of software code that is responsible for the failure.
Conventional debugging techniques include steps of inserting output statements after subsections of code to notify the developer of the results either before, during or after the execution of the remainder of the program. By incorporating output statements into the code, the developer can more quickly deduce the part or parts of code that are yielding the wrong in-process answer, thereby achieving fault isolation to the respective subsection of code. The software developer frequently employees a standard case to test and debug the code. Using a standard case, the software developer can test each result from each output statement in the code for accuracy, by comparing each result with an expected result for the standard case.
Although the process of debugging has been automated to some extent through the use of error codes and commercial debuggers for popular development languages, the process of debugging remains a very time consuming and costly part of the software development process.
Even after the software is developed, it must be verified and validated. Software verification and validation generally encompasses an acceptance process in which the software is functionally verified to be correct when its operation is compared to the required performance defined in the design specification. Operational characteristics of the software are verified within the bounds of the development specification. The verification and validation step is typically implemented both internally to the software development establishment and by the ultimate customer, such as the federal government. For example, the U.S. Department of Defense may have a software product delivered to control a missile. The U.S. Department of Defense in this instance would obviously be interested in conducting an independent verification of the functionality of the software.
The process of verifying the operation of software under all operational modes is typically a very time-consuming and costly effort, in which all possible scenarios are executed for the software, to identify its response under all conditions. The conventional approach comprises a user stepping through operational modes and measuring a software's responses. By doing so, the user can verify the software's functionality with some certainty, thereby validating it for operation in the intended application. The amount of effort required for software verification and validation is typically augmented by a user implementing extensive examination of each line of the software code. This line-by-line examination of the software code, in addition to other available techniques, is typically implemented to ensure that the software will operate properly under all operational modes. Proper functionality of the software code should include performance reliability and robust operation. Efforts continue in the prior art for enhancing the efficiency and efficacy of software debugging, verification and validation procedures, which typically must be implemented both during and after the design phase of the software is completed.
SUMMARY OF THE INVENTION
The method and apparatus of the present invention present new approaches for software debugging, verification and validation. The present invention utilizes a knowledge-based reasoning approach to build a functional model of the software code for identifying and isolating failures in the software code. The knowledge-based reasoning approach of the present invention uses the software design, which is preferably based upon a flow chart or block diagram representation of the software functionality, to build the functional model. The software block diagram contributes to the functional model by defining the inputs and outputs of the various blocks of code, as well as defining data interconnections between the various blocks of code. In accordance with a method of the present invention, test points are strategically inserted throughout the code, wherein each test point is associated with a corresponding block of code. A standard case is used to determine the expected values of the test points for an expected proper-operation execution of the software code.
The software code is then executed, and the actual values of the test points from the program execution are compared with the expected values of the test points. Failed test points which do not agree with corresponding expected values are thus determined. The functional model, which includes information functionally relating the various test points to one another, is then used to isolate the failed test points to one or more conclusive sources of failure within the code.
In accordance with one aspect of the present invention, a method of selecting a source failure test point from a plurality of test points in a computer program comprises an initial step of providing a plurality of test points in the computer program, and a subsequent step of defining at least one fault propagation path. (In another aspect of the present invention, the fault propagation path is referred to as a data propagation path.) The test points are placed into the code of the computer program, and an order of data flow among the test points is determined. The order of data flow defines at least one fault propagation path through the plurality of test points. The source failure test point is defined as having a highest probability relative to other test points in the computer program of being a source of failure. The at least one fault propagation path associates at least two of the plurality of test points and an order of data flow and data dependency within the computer program.
The method of the present invention includes a step of generating a standard case for the test points of the computer program in which expected values of the test points for an expected proper-operation execution of the computer program are generated. The computer program is then executed on a computer, and the actual values of the test points from the program execution are compared with the expected values of the test points. Failed test points which do not agree with corresponding expected values are determined. An additional step is provided for finding the source failure test point that is earliest (relative to other failure test points in the at least one fault propagation path) in an order of data flow and data dependency. The failure test points are associated with the at least one data propagation path, and the step of finding the source failure test point that is earliest includes a step of selecting the failed test point which is earliest in the at least one fault propagation path.
Another aspect of the present invention includes a method of determining a source of failure test point from a plurality of test points in a computer program. The source of failure test point has a highest probability relative to other test points in the computer program of being a source of failure. The method includes a step of determining a sequential flow of data among a plurality of test points in the computer program, and a step of ranking the plurality of test points, using the determined sequential flow of data, in an order of an earliest test point in the determined sequential flow of data to a last test point in the determined sequential flow of data, to thereby generate a ranked set of test points. (In

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for debugging, verifying and validating... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for debugging, verifying and validating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for debugging, verifying and validating... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2472478

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.