Method and apparatus for DC offset cancellation in amplifiers

Details Method and apparatus for DC offset cancellation in amplifiers Method and apparatus for DC offset cancellation in amplifiers

2008-03-25

2008-03-25

Choe, Henry (Department: 2817)

Amplifiers

With periodic switching input-output

C330S069000

Reexamination Certificate

active

07348839

ABSTRACT:
A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.

REFERENCES:
patent: 3810031 (1974-05-01), Poujois
patent: 6911864 (2005-06-01), Bakker et al.
patent: 7262654 (2007-08-01), Kejariwal et al.

Affiliated with

Also associated with

Rating

Method and apparatus for DC offset cancellation in amplifiers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for DC offset cancellation in amplifiers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for DC offset cancellation in amplifiers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2815523