Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
2000-01-26
2004-06-29
Vincent, David (Department: 2661)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C386S349000
Reexamination Certificate
active
06757304
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communication systems and methods, and more particularly relates to a data communication system and method capable of reducing time lag when data is exchanged among various types of buses via networks.
2. Description of the Related Art
FIG. 1
shows an example of the configuration of a conventional network system. In this network system, a digital video cassette recorder (DVCR)
11
is connected to an IEEE1394 (“Institute of Electrical and Electronic Engineers”) serial bus (hereinafter simply referred to as a 1394 serial bus)
12
. The 1394 serial bus
12
is connected to an asynchronous transfer mode (ATM) network
15
via a User Network Interface (UNI)
14
from an ATM/1394 repeater
13
. The ATM network
15
is connected via a UNI
16
to an ATM/1394 repeater
17
. The ATM/1394 repeater
17
is connected via a 1394 serial bus
18
to a DVCR
19
.
In the 1394 serial bus
12
(as well as the serial bus
18
), data is transmitted as shown in
FIG. 2. A
source packet as shown by (A) in
FIG. 2
contains data from the DVCR
11
and is disassembled into data blocks of 480-byte units as shown by (B) in FIG.
2
. These data blocks have an isochronous packet header and a common isochronous packet (CIP) header attached thereto which are transmitted in cycles as isochronous packets with a predetermined timing in a period of 125 &mgr;s. A cycle-start packet is transmitted from the cycle master at the start of each cycle. In order to establish synchronization with other devices on the 1394 serial bus
12
, every device on the 1394 serial bus
12
has a 32 bit cycle-time register therein. Each device operates, while being synchronized every 125 &mgr;s with the value of the cycle-time register thereof by causing the value of the cycle-time register thereof to be reflected by the value of cycle time data of the cycle-start packet (namely, the value of the cycle-time register of the cycle master) which is synchronized with a reference clock frequency of 24.576 MHz (hereinafter referred to as a “bus reference clock”) of the cycle master. Accordingly, the ATM/1394 repeater
13
also operates at a place where interface processing between the 1394 serial bus
12
and the ATM/1394 repeater
13
is required, while being synchronized with the value of the cycle-time register.
The 1394 interface unit of the ATM/1394 repeater
13
performs interface processing on the packet data and an ATM interface unit of the ATM/1394 repeater
13
converts the processed packet data into ATM cells. The ATM cells are transmitted via the UNI
14
to the ATM network
15
which operates, while being synchronized with a reference clock frequency of 8 kHz (hereinafter referred to as an ATM reference clock) so as to be synchronized with every device connected thereto. Therefore, the ATM interface unit of the ATM/1394 repeater
13
performs various types of processing synchronized with the ATM reference clock.
The ATM cells are transmitted via the ATM network
15
and the UNI
16
to the ATM/1394 repeater
17
. The input ATM cells are reassembled at an ATM interface unit of the ATM/1394 repeater
17
. The reassembled data is transmitted to a 1394 interface unit of the ATM/1394 repeater
17
where the data are formed into packets. Then the packet data is transmitted via the 1394 serial bus
18
to the DVCR
19
. The ATM interface unit of the ATM/1394 repeater
17
operates, while being synchronized with the ATM reference clock of the ATM network
15
while the 1394 interface unit of the ATM/1394 repeater
17
operates, while being synchronization of the value of the cycle-time register with that of every device connected to the 1394 serial bus
18
.
FIGS. 3
is a theoretical timing chart in a case in which, as described above, the data of the DVCR
11
on the 1394 serial bus
12
is transmitted via the ATM network
15
to the DVCR
19
on the 1394 serial bus
18
. When the output data of the DVCR
11
is, for example, NTSC (“National Television System Committee”) standard image data, 29.97 Hz frame synchronizing signals are sampled at the 24.576 MHz bus reference clock, for example, at time t
1
, t
4
, and t
7
(shown by (A) in FIG.
3
).
The image data sampled at time t
1
is transmitted from the DVCR
11
to the 1394 serial bus
12
by the bus cycle which starts at time t
2
. At this time, a time stamp is attached to a CIP packet CIP
1
(shown by (B) in FIG.
3
).
As shown in
FIG. 4
, an isochronous packet, which is transmitted via the 1394 serial bus
12
, includes a 1394 header, a CIPHeader
1
, a CIPHeader
2
, and data. The CIPHeader
2
contains 16-bit time information SyncTime as the time stamp which is equal to the lower 16 bits of the cycle-time register of any device on the 1394 serial bus
12
. The time stamp of the CIP packet CIP
1
is obtained by adding the value of an additional delay time TdelayAdd to the value of the cycle-time register at the sampling time (time t
1
). In other words, the time stamp corresponds to time t
3
which is the additional delay time TdelayAdd after time t
1
. The additional delay time TdelayAdd corresponds to the time for absorbing jitters, such as cycle-timing shift of the 1394 serial bus
12
.
When the CIP packet CIP
1
is transmitted to the DVR
19
via the 1394 serial bus
18
, the DVCR
19
fetches the time stamp contained in the packet (shown by (C) in FIG.
3
). Since the time stamp corresponds to time t
3
, the DVCR
19
generates a frame synchronizing signal for the first frame at time t
3
. The same processing is sequentially applied to the second frame, the third frame, and so on, one after another.
The timing charts shown in
FIG. 3
are theoretical, and an actual timing chart is shown in FIG.
5
. That is, the synchronizing signal for the first frame sampled at time t
1
is transmitted at time t
2
to the 1394 serial bus
12
as the CIP packet CIP
1
which includes the time stamp corresponding to time t
3
obtained by adding the additional delay time TdelayAdd to the sampling time t
1
. The CIP packet CIP
1
is delayed by a delay time TdelayNet
1
which is the total delay time accumulated on each transmission line of the 1394 serial bus
12
, the ATM/1394 repeater
13
, the UNI
14
, the ATM network
15
, the UNI
16
, ATM/1394 repeater
17
, and the 1394 serial bus
18
. Finally, the DVCR
19
receives the CIP packet CIP
1
at the timing of the bus cycle which starts at time t
4
. The DVCR
19
fetches the time stamp from the CIP packet CIP
1
(shown by (C) in
FIG. 5
) and generates a synchronizing signal for the first frame at time t
6
corresponding to the fetched time stamp (shown by (D) in FIG.
5
).
The DVCR
19
connected to the 1394 serial bus
18
on the receiver side times a time ToffsetAddCount
1
#
2
between time t
4
and time t
6
using the bus reference clock of the 1394 serial bus
18
on the receiver side. Whereas, the DVCR
11
connected to the 1394 serial bus
12
on the sender side sets, as the time stamp of the CIP packet CIP
1
, time t
3
which is a time ToffsetAddCount
1
#
1
after the start time t
2
of a bus cycle using the bus reference clock of the 1394 serial bus
12
(shown by (A) in FIG.
5
). The time ToffsetAddCount
1
#
1
corresponds to a time difference between time t
3
and time t
2
, in other words, a time difference between time t
5
which is a time TdelayNet
1
after time t
3
, and t
4
which is the time TdelayNet
1
after time t
2
(shown by (B) in FIG.
5
).
Because the bus reference clock of the 1394 serial bus
12
on the sender side and that of the 1394 serial bus
18
on the receiver side are not synchronized, the cycle of the 1394 serial bus
12
(shown by (B) in
FIG. 5
) does not exactly correspond to that of the 1394 serial bus
18
(shown by (C) in FIG.
5
). Accordingly, a time TsndFrame between time t
3
and time t
9
as the frame cycle of the 1394 serial bus
12
(shown by (B) in
FIG. 5
) does not correspond to a time TrevFrame between time t
6
and time t
13
as the frame cycle of the 1394 serial bus
18
(sh
Maruyama Atsushi
Nomura Takashi
Frommer William S.
Frommer & Lawrence & Haug LLP
Polito Bruno
Sony Corporation
Vincent David
LandOfFree
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