Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-04-20
2002-11-05
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S068000, C341S069000
Reexamination Certificate
active
06476748
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to the field of digital to analog conversion. In particular, the invention relates to implementing cyclic return to zero techniques for digital to analog converters.
2. Description of Related Art
Ideally, a digital-to-analog converter (DAC) with a continuous-time output (e.g., a zero-order-hold output as opposed to a switched-capacitor output) converts an input signal, represented as a sequence of digital numbers, into an analog output waveform, represented as a time-varying voltage or current, without introducing any error. However, practical DACs introduce error consisting of random noise, linear distortion, and nonlinear distortion. The term noise is generally used to denote error that is not correlated with the DAC input signal, the term linear distortion is generally used to denote error that is linearly related to the input signal, and the term nonlinear distortion (also called harmonic distortion) is generally used to denote error that is nonlinearly related to the input signal.
In high precision DACs with continuous-time outputs, the overall DAC error is often dominated by nonlinear distortion. However, in many applications, such as high-fidelity audio systems and transmitters for wireless communications, nonlinear distortion of a given power is more problematic than noise and linear distortion of comparable power. Unfortunately, to avoid introducing nonlinear distortion it is not only necessary for the DAC output to settle to the correct output level by the end of each sample period, but the transient associated with the settling process must not contain nonlinear distortion. In many high-performance DACs with continuous-time outputs, nonlinear transient settling behavior is the dominant source of nonlinear distortion.
For example, assume x[n] represents the digital input sequence to a given DAC, and assume y(t) represents the continuous-time analog output waveform generated by the DAC in response to x[n]. Since x[n] is a discrete-time sequence, and y(t) is a continuous-time function, a DAC performs interpolation to convert the sequence of discrete numbers into a continuous-time waveform. A common type of interpolation used is zero-order-hold interpolation, which sets y(t)=&agr;x[n]+&bgr; during each sample interval, i.e., during nT≦t<(n+1)T for each integer n, where &agr; is a constant scale factor, &bgr; is a constant offset, and T is the sample period of the input sequence. In this case, during each sample interval, y(t) is held constant at a level which, neglecting the constant offset, is proportional to the corresponding discrete value of the input sequence. At the end of each sample interval, i.e., at each time (n+1)T, the output waveform abruptly jumps to the level corresponding to the next input sample value, i.e., &agr;x[n+1]+&bgr;.
Since no physical device can generate a truly discontinuous waveform, zero-order-hold interpolation is an idealization; i.e. practical DACs can only approximate the zero-order-hold behavior. Therefore, a transient error waveform can be defined as the difference between the actual interpolation function implemented by the DAC and ideal zero-order-hold interpolation. In many DACs, it is also possible to define a discrete error sequence that represents errors not associated with the interpolation process such as often arise from component mismatches. Therefore, in general the output of the DAC is given by
y
(
t
)=&agr;
x[n]+&bgr;+e
d
[n]+e
l
(
t
),
nT≦t
<(
n
+1)
T,
(1)
for each value of n, where e
d
[n] is the discrete error and e
l
(t) is the transient error. Well known techniques such as dynamic element matching can be used to reduce nonlinear distortion contributed by the discrete error sequence of the DAC if necessary. Therefore, to simplify the presentation the discrete error sequence is ignored or assumed to be zero throughout much of the patent. To further simplify the presentation, the DAC offset, &bgr;, is assumed to be zero without loss of generality.
FIG. 1
provides a comparison between representative continuous-time output waveforms from an idealized DAC with ideal zero-order-hold interpolation, and from a typical practical DAC that only approximates zero-order-hold interpolation. More particularly,
FIG. 1
shows representative continuous-time DAC output waveforms: the top waveform
102
corresponds to ideal zero-order-hold interpolation, the middle waveform
104
represents the approximate zero-order-hold interpolation typically implemented by practical DACs, and the bottom waveform
106
represents the transient error between the actual and ideal interpolations. The bottom waveform
106
is the transient error associated with the practical DAC; i.e. it is the difference between the top and middle waveforms
102
and
104
, respectively. As is illustrated in
FIG. 1
, a the transient error consists of a train of transient pulses each of which starts at the beginning of a sample period and asymptotically approaches zero. It should be noted that if the discrete error sequence were not zero, the transient pulse originating in the n
th
sample period would asymptotically approach e
d
[n]. Therefore, the transient error can be written in the form:
e
t
(
t
)
=
∑
n
=
-
∞
∞
p
n
(
t
-
nT
)
,
(
2
)
Where p
n
(t) is the transient pulse associated with the n
th
sample interval. Typically, p
n
(t) is causal, has a peak at t=0, and has a shape that depends nonlinearly on both the (n−1)
th
and n
th
DAC input samples.
As discussed previously, it is desirable to avoid having the transient error introduce nonlinear distortion. Therefore, it is undesirable to have a nonlinear relationship between the transient pulses and the DAC input values. In general, it is not possible to eliminate the transient pulses, but it is possible to design a DAC with transient error that consists of uniformly shaped and spaced transient pulses each of which is scaled by the corresponding input sequence sample. To the extent that this is done, nonlinear distortion is eliminated from the transient error. Two prior art methods of achieving this result will now be discussed.
Both of the prior art methods involve multiple one-bit DACs, i.e., DACs whose inputs are one-bit sequences, which are combined to yield a composite multi-bit DAC.
FIG. 2
is a block diagram illustrating an exemplary composite DAC
200
comprising eight one-bit DACs
202
1
-
202
8
and summing operation
206
that can be utilized in implementing the two prior art methods. The overall DAC input, x[n], is a sequence of 4-bit numbers each of which is restricted to the set {−4, −3, −2, −1, 0, 1, 2, 3, 4}. It is assumed that the four input bits in
FIG. 2
have weights −4, 2, 1, and 1, respectively, which can be thought of as a conventional 3-bit two's complement number with an extra least-significant bit. A digital logic block, such as digital encoder
204
, converts each input sample to a unity weighted 8-bit number representation in which the value of each bit is taken to be ½ when the bit is high and −½ when the bit is low. The digital encoder
204
selects the 8 bits such that the sum of the resulting bit values is equal to x[n]. For example, if x[n]=2, the digital encoder sets six of the bits labeled x
i
[n] in
FIG. 2
high, and the remaining two bits low. It can be verified that if each one-bit DAC performs ideal zero-order-hold interpolation with an output value of &Dgr;/2 when the input bit is high and −&Dgr;/2 when the input bit is low, then the overall DAC is an ideal zero-order-hold DAC with an output that ranges from −4&Dgr; to 4&Dgr; in steps of &Dgr;. Alternatively, if x[n] is restricted to the range {0, 1, . . . , 8}, the digital encoder s
Blakely , Sokoloff, Taylor & Zafman LLP
Nguyen Khai
Silicon Wave Inc.
Tokar Michael
LandOfFree
Method and apparatus for cyclic return to zero techniques... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for cyclic return to zero techniques..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for cyclic return to zero techniques... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2992497