Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-09-05
2006-09-05
Rodriguez, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07103524
ABSTRACT:
A system for using machine learning based upon Bayesian inference using a hybrid Monte Carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Then, for each of the smaller simpler extraction problems, complex mathematical models are created using machine learning techniques. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system uses Bayesian inference implemented with a hybrid Monte Carlo method to train a set of neural networks for extraction problems. After the creation of a set of models for each of the smaller simpler extraction problems, the machine-learning based models may be used for extraction.
REFERENCES:
patent: 4300196 (1981-11-01), Lopresti
patent: 4839823 (1989-06-01), Matsumoto
patent: 5276632 (1994-01-01), Corwin et al.
patent: 5452224 (1995-09-01), Smith et al.
patent: 5642296 (1997-06-01), Saxena
patent: 5678020 (1997-10-01), Singh et al.
patent: 5689621 (1997-11-01), Salam et al.
patent: 5808919 (1998-09-01), Preist et al.
patent: 5822218 (1998-10-01), Moosa et al.
patent: 5901063 (1999-05-01), Chang et al.
patent: 5903469 (1999-05-01), Ho
patent: 6018623 (2000-01-01), Chang et al.
patent: 6038338 (2000-03-01), Nguyen
patent: 6038383 (2000-03-01), Young et al.
patent: 6061508 (2000-05-01), Mehrotra et al.
patent: 6128768 (2000-10-01), Ho
patent: 6182269 (2001-01-01), Laubhan
patent: 6189131 (2001-02-01), Graef et al.
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6212492 (2001-04-01), Kuge
patent: 6243653 (2001-06-01), Findley
patent: 6304836 (2001-10-01), Krivokapic et al.
patent: 6304837 (2001-10-01), Geiger et al.
patent: 6311312 (2001-10-01), Chang et al.
patent: 6327556 (2001-12-01), Geiger et al.
patent: 6381555 (2002-04-01), Sewell
patent: 6412097 (2002-06-01), Kikuchi et al.
patent: 6414498 (2002-07-01), Chen
patent: 6430729 (2002-08-01), Dewey et al.
patent: 6446027 (2002-09-01), O Keefe et al.
patent: 6526549 (2003-02-01), You
patent: 6543035 (2003-04-01), Ohba et al.
patent: 6549854 (2003-04-01), Malinverno et al.
patent: 6581195 (2003-06-01), Tanaka
patent: 6581198 (2003-06-01), Teig et al.
patent: 6584456 (2003-06-01), Dom et al.
patent: 6587997 (2003-07-01), Chen et al.
patent: 6609237 (2003-08-01), Hamawaki et al.
patent: 6671661 (2003-12-01), Bishop
patent: 6687887 (2004-02-01), Teig et al.
patent: 6725439 (2004-04-01), Homsinger et al.
patent: 6735748 (2004-05-01), Teig et al.
patent: 2002/0010691 (2002-01-01), Chen
patent: 2002/0056070 (2002-05-01), Tanaka
patent: 2002/0075383 (2002-06-01), Trobaugh et al.
patent: 2003/0065535 (2003-04-01), Karlov et al.
patent: 2003/0236760 (2003-12-01), Nugent
patent: 2004/0049751 (2004-03-01), Teig et al.
Papadopoulos et al., “Hierarchical Bayes Estimation for the Exponential-Multinomial Model in Reliability and Competing Risk”. p. 477-484 1996.
Chick-S.E., Bayesian Analysis for Simulation Input and Output. 1997 Winter Simulation Conference. p. 253-260.
Pullela et al., “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization” ACM/IEEE 1993 p. 165-170.
Woodburn et al., “Computing with Uncertainty in Probabilistic Neural Networks on Silicon” May 2000. p. 1-17.
Neal-R.M., “Monte Carlo Implementation of Gaussian Process Models for Bayesian Regression and Classification” Univ. of Toronto 1997 p. 1-24.
U.S. Appl. No. 10/335,247, filed Dec. 31, 2002, Steven Teig et al., CIP of U.S. Appl. No. 10/062,264.
U.S. Appl. No. 10/335,097, filed Dec. 31, 2002, Steven Teig et al., CIP of U.S. Appl. No. 10/062,264.
U.S. Appl. No. 10/335,248, filed Dec. 31, 2002, Steven Teig et al., CIP of U.S. Appl. No. 10/062,264.
U.S. Appl. No. 10/335,095, filed Dec. 31, 2002, Steven Teig et al., CIP of U.S. Appl. No. 10/062,264.
U.S. Appl. No. 10/334,664, filed Dec. 31, 2002, Steven Teig et al., CIP of U.S. Appl. No. 10/062,264.
U.S. Appl. No. 10/062,264, filed Jan. 31, 2002, Steven Teig et al., Application filed on the same day as the present application with the same specification and drawings.
U.S. Appl. No. 10/061,945, filed Jan. 31, 2002, Steven Teig et al., Application filed on the same day as the present application with the same specification and drawings.
U.S. Appl. No. 10/062,184, filed Jan. 31, 2002, Steven Teig et al., Application filed on the same day as the present application with the same specification and drawings.
U.S. Appl. No. 10/066,326, filed Jan. 31, 2002, Steven Teig et al., Application filed on the same day as the present application with the same specification and drawings.
U.S. Appl. No. 10/062,193, filed Jan. 31, 2002, Steven Teig et al., Application filed on the same day as the present application with the same specification and drawings.
Brambilla, A. et al., Statistical Method for the Analysis of Interconnects Delay in Submicrometer Layouts, IEEE, Aug. 2001, pp. 957-966.
Brandt et al., Circuit Multi-fault Diagnosis and Prediction Error Estimation Using a Committee of Bayesian Neutral Networks, IEEE, Colloquium on Testing Mixed Signal Circuits and Systems, Oct. 23, 1997, pp. 7/1-7/7.
Fertig, “Extracting Knowledge from Case Databases”, Apr. 1991, IEEE Proceedings on Seventeenth Annual Northeast Bioengineering Conference, pp. 267-268.
Hung et al., Machine Learning in Engineering Design—an Unsupervised Fuzzy Neural Network Case-based Learning Model, Dec. 1997, IEEE Proceeding, Intelligent Information System, pp. 156-160.
Hunter, Knowledge Acquisition Planning for Inference from Large Databases, Jan. 1990, IEEE Proceeding of the 23th Annual Hawaii International Conference on System Sciences, vol. 2, pp. 35-44.
Ida et al., Bayesian Analysis in Manufacturing Instrumentation for Test and Evaluation, IEEE, Conference record of 1993 Fourth Fifth Annual Conference of Electrical Engineering Problems and Plastics Industries, Apr. 27, 1993, pp. 4-13.
Kolehmainen et al., A Bayesian Approach and Total Variation Priors in 3D Electrical Impedance Tomography, Proceedings of the 20th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, vol. 2, Oct. 29, 1998, pp. 1028-1031.
Li et al., Monte Carlo Simulation Techniques for Probabilistic Tracking, IEEE, 2001, pp. 75-82.
Li et al., Pre-extracting Support Vectors for Support Vector Machine, Aug. 2000, IEEE Proceedings of 5th International Conference on Signal Processing, vol. 3, pp. 1432-1435.
Mani, N., A Neural Network Model for Partitioning in Floorplan Design, IEEE, pp. 1676-1680.
Niu et al., A Bayesian Approach to Variable screening for Modeling the IC Fabrication Process, 1995, IEEE International Symposium on Circuits and Systems, vol. 2, Apr. 30, 1995, pp. 1227-1230.
NN9107436, Maximum Likelihood Training of Probabilistic Linear Functions (Probabilistic Perceptrons), IBM Technical Disclosure Bulletin, vol. 34, No. 2, Jul. 1991. pp. 436-442.
Ruping, S., Incremental Learning with Support Vector Machines, Dec. 2001, IEEE Proceedings of Internal Conference on Data Mining, pp. 641-642.
Suykens, Nonlinear Modelling and Support Vector Machines, May 2001, IEEE Proceedings of the 18thInstrumentation and Measurement Technology Conference, vol. 1, pp. 287-294.
Vehtari et al., Bayesian Neural networks for Industrial Applications, Proceedings of the 1999 IEEE Midnight-Sun Workshop on Soft Computing Methods in Industrial Applications, Jun. 16, 1999, pp. 63-68.
Wang et al., Accurate Parasitic Resistance Extraction for Interconnection Analysis, 1995,
Chatterjee Arindam
Teig Steven
Cadence Design Systems Inc.
Rodriguez Paul L.
Stattler Johansen & Adeli LLP
Stevens Tom
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