Method and apparatus for CRC computation

Details Method and apparatus for CRC computation Method and apparatus for CRC computation

1988-12-06

1992-07-14

Baker, Stephen M.

Excavating

371 53, H03M 1300

Patent

active

051309912

ABSTRACT:
In a CRC computation system, when 1-byte data is established on one of two buses, the 1-byte data is selected for a 1-byte-wise CRC computation, and when 1-byte data are established on both of the two buses, the 2-byte data are selected for a 2-byte-wise CRC computation. Either 1-byte data or 2-byte data as a result of the CRC computation is selected in accordance with a data selecting signal and held in accordance with a data holding signal.

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Weissberger, A., "An LSI Implementation of an Intelligent CRC Computer . . . ", IEEE Jour. of Solid-State Circuits, vol. SC-15, No. 1, Feb. 1980, pp. 52-60.
Helness, K., "Implementation of a Parallel Cyclic Redundancy Check Generator", Compouter DEsign, Mar. 1974, pp. 91-96.
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Ramabadran, T. et al., "A Tutorial On CRC Computations", IEEE Micro, Aug. 1988, pp. 62-74.
IBM, TDM, vol. 27, No. 6, Nov. 1964, pp. 3572-3576, "Method for High-Speed CRC Computation", Nielson.

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