Patent
1993-04-30
1995-02-07
Lall, Parshotam S.
G06F 930
Patent
active
053882334
ABSTRACT:
A counter for counting instructions is implemented in a computer system having a processor in which instructions are fetched for potential execution. Each instruction is characterized by at least one instruction attribute. The counter includes at least one bit map register for storing a bit map. Each map bit position in the bit map represents a particular instruction attribute. Map bits at predetermined map bit positions are set. A bit mask register stores a bit mask corresponding to a fetched instruction. Each mask bit position in the bit mask represents a particular instruction attribute. A mask bit at a mask bit position is set if the mask bit position represents an instruction attribute of the fetched instruction. Logic circuitry increments a count value associated with a bit map based upon a comparison of the bit map with the bit mask.
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Hays Kirk I.
Smith Wayne D.
Intel Corporation
Lall Parshotam S.
Vu Viet
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