Method and apparatus for correction errors in a memory

Details Method and apparatus for correction errors in a memory Method and apparatus for correction errors in a memory

1993-11-18

1996-04-23

Gordon, Paul P.

Excavating

371 402, G06F 1110

Patent

active

055110789

ABSTRACT:
The method and apparatus for correcting one B-bit block in error in a memory organized in words comprising N B-bit blocks consist of appending to the data bits to be written into the memory words a limited number of error correction bits computed from a depopulated parity check matrix which gives the capability of only correcting one block in error and improving the memory failure rate by cyclically reading each word, correcting a block found in error if any and writing the corrected data bits with the corresponding error correction bits in place of the read word.

REFERENCES:
patent: 3766521 (1973-10-01), Carter et al.
patent: 4761785 (1988-08-01), Clark et al.
patent: 4964129 (1990-10-01), Bowden, III et al.
8153 Computer, Jul. 23, 1990, No. 7, Los Alamitos, CA, US "Error Control Coding in Computers by Fujiwara", Pradhan, pp. 63-72.

Affiliated with

Also associated with

Rating

Method and apparatus for correction errors in a memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for correction errors in a memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for correction errors in a memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2315219