Method and apparatus for correcting the phase of a clock in...

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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C375S316000, C375S239000, C375S286000, C329S304000

Reexamination Certificate

active

07065160

ABSTRACT:
A method for correcting the phase of a clock in a data receiver which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) or a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single signal values (1,0) of different signal levels.

REFERENCES:
patent: 3820051 (1974-06-01), Puckette
patent: 4308500 (1981-12-01), Avins
patent: 4535459 (1985-08-01), Hogge
patent: 6034554 (2000-03-01), Francis
patent: 0 585 090 (1993-08-01), None
patent: WO 00/38324 (2000-06-01), None
J. D. H. Alexander, “Clock Recovery From Random Binary Signals”,Electronic Letters,vol. 11, (Oct. 1975), pp. 541-542.

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