Method and apparatus for correcting errors in digital signals ha

Details Method and apparatus for correcting errors in digital signals ha Method and apparatus for correcting errors in digital signals ha

1988-05-24

1990-04-03

Atkinson, Charles E.

Excavating

360 53, G06F 1110, G11C 2900

Patent

active

049146610

ABSTRACT:
8-bit data words and check words of a data block are supplied to an error recognition circuit the same time that they are written into a FIFO storage unit a word clock rate derived from the signals reproduced from a magnetic tape record which are subject to phase fluctuations. At the same time a counter is advanced by the same clock pulses. The error recognition circuit forms syndrome words by which each erroneous data word can be located and its address stored, as the state of the counter, into a register which is capable of registering more than one such address. The error recognition circuit also generates an error pattern multibit signal which is likewise stored in a register which can store more than one error pattern. Clock pulses of the same frequency as the write-in pulses but without fluctuations in phase are generated for read out of data blocks from the FIFO storage unit and for producing a train of pulses for clocking a second counter, the state of which is compared with the address or addresses stored in the first register, so that at the same time an erroneous word is read out from the FIFO unit the corresponding error pattern will be combined with the erroneous data word in an XOR correlation to provide the necessary correction of the erroneous word.

REFERENCES:
patent: 3778787 (1973-12-01), Cannon
patent: 4254500 (1981-03-01), Brookhart
patent: 4682332 (1987-07-01), Okamoto
patent: 4763332 (1988-08-01), Glover
patent: 4775978 (1988-10-01), Hartness

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