Method and apparatus for correcting errors in convolutional code

Details Method and apparatus for correcting errors in convolutional code Method and apparatus for correcting errors in convolutional code

1988-07-25

1990-06-05

Lastova, John R.

Excavating

371 53, G06F 1100

Patent

active

049320297

ABSTRACT:
A method and apparatus for correcting errors in convolutional code signals prior to Viterbi decoding. Branch metrics in the decoding of n-PSK convolution code signals are used to obtain a differential metric with calculations in both the logical and arithmetic domain. The differential metric is used to obtain a phase error signal which includes information on the quality of the convolution code signals, and control signals for the resolution of phase ambiguity in the demodulation of the convolution code signals are obtained using the phase error signal, such that an improvement in the bit error rate and synchronization is made possible, in particular in decoders for error-correctable convolution code signals. The phase error signal is produced when, over a predetermined time period the differential metric is less than a given threshold value or is decreasing, so as to indicate an error in the demodulated convolution signal over such time period and therefore the probable presence of a phase error. The phase error signals are used to estimate the presence and direction of phase angle jumps in the modulation carrier by formation of the difference between current and previously ascertained values of the phase angle, starting of a counter for upward counting of the binary value of the signal whenever the phase angle jump direction is positive, starting of this counter for downward counting of the binary value whenever the phase angle jump direction is negative, and emission of the counter state in the form of a control signal.

REFERENCES:
patent: 3891959 (1975-06-01), Tsuji
patent: 4483012 (1984-11-01), Wei
patent: 4566100 (1986-01-01), Mizuno
patent: 4675871 (1987-06-01), Gordon
patent: 4757506 (1988-07-01), Heichler
Orndorff et al., "Viterbi Decoder VLSI Integrated Circuit for Bit Error Correction", NTC'81, vol. 3.
Proc. of IEEE, vol. 61, #3, Mar. 1973, (pp. 263-277).

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