Method and apparatus for correcting a multilevel cell memory by

Details Method and apparatus for correcting a multilevel cell memory by Method and apparatus for correcting a multilevel cell memory by

1996-09-06

1998-05-19

Baker, Stephen M.

Excavating

G11C 2900

Patent

active

057545669

ABSTRACT:
A method and apparatus for correcting errors in a multilevel cell memory is described. A multilevel cell memory is comprised of multilevel cells, each capable of storing two or more bits of data. A plurality of data bits is received by the multilevel cell memory. The plurality of data bits are sorted into two or more data words. Error correction codes are generated for each of the two or more data words. A memory element bit pattern is formed that comprises one bit from each of the two or more data words. A charge state associated with the memory element bit pattern is stored in one of the multilevel cells.

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