Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2007-06-12
2007-06-12
Patel, Nitin I. (Department: 2629)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S212000
Reexamination Certificate
active
10287580
ABSTRACT:
In a signal coordinating method and apparatus, a pulse generating circuit receives a VSYNC signal and generates a plurality of critical pulses that define critical time periods from fields can control edges of the VSYNC signal. A determining circuit receives an HSYNC signal and the critical pulses, and generates a trigger signal upon detecting that a line scan control edge of the HSYNC signal appears during one of the critical time periods. A time delay loop introduces a time delay into the VSYNC signal upon receipt of the trigger signal to cause the critical time period to appear after the line scan control edge of the HSYNC signal.
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Chen Chien-Chou
Wang Jui-Ming
Amtran Technology Co. Ltd.
Morgan & Lewis & Bockius, LLP
Patel Nitin I.
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