Method and apparatus for coordinating execution of an instructio

Boots – shoes – and leggings

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G06F 900

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047317361

ABSTRACT:
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

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patent: 4547849 (1985-10-01), Louie et al.
Zilog, 1981 Data Book, pp. 105-112, 120-127, 397-410.
National Semiconductor, "NS16082 Memory Management Unit (MMU)", Mar. 1982.
National Semiconductor, "NS16081 Floating-Point Unit", Oct. 1982.
National Semiconductor, "NS16032S-6, NS16032S-4 High-Performance Microprocessors", Nov. 1982.

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