Computer graphics processing and selective visual display system – Display driving control circuitry – Adjusting display pixel size or pixels per given area
Reexamination Certificate
2000-07-05
2003-06-10
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Adjusting display pixel size or pixels per given area
C345S699000, C345S204000, C348S521000, C348S543000, C348S542000
Reexamination Certificate
active
06577322
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for converting a digital video signal output from a personal computer or the like into a signal having a resolution that matches a display device.
2. Description of the Related Art
The resolution of an LCD (liquid crystal display) panel is physically fixed; for example, in the case of a panel designed for VGA (Video Graphics Array) which is one of the video display standards, since the screen is formed in a matrix of 640 pixels horizontally and 480 pixels vertically, a correct image cannot be displayed unless a video signal consisting of 640×480 pixel data per screen is supplied by synchronizing its timing with horizontal and vertical sync signals. In the case of an XGA (Extended Graphics Array) panel, the matrix size is 1024×768 pixels.
If the number of pixels in an image to be displayed on such a display panel of fixed pixel arrangement is different from the number of pixels of the panel, the pixel density of the input image data must be converted to match that of the panel before presenting the data to the panel for display. For example, when transmitting VGA video data for display on an XGA panel, the pixel density must be scaled up by a factor of 1.6 in both horizontal and vertical directions.
The simplest method of pixel density conversion will be described by taking a scaling in the horizontal direction as an example. When converting VGA data to XGA data, for example, eight pixel data should be generated from five pixel data because the pixel density must be scaled up by a factor of 1.6. More specifically, an input data sequence of D
1
, D
2
, D
3
, D
4
, D
5
, D
6
, and so on is converted, for example, into an output data sequence of D
1
, D
1
, D
2
, D
2
, D
3
, D
4
, D
4
, D
5
, D
6
, D
6
, and so on by duplicating three of the five pixel data.
When the resolution of the input video data is unknown, the resolution must be identified before converting the pixel density. In a prior art method which converts an analog RGB video signal into digital form for display on a display device such as an LCD panel, a microcomputer or the like examines the kind, or the resolution, of the video signal based on the horizontal and vertical sync signals accompanying the video signal, and controls a pixel density conversion circuit to convert the resolution of the video signal to the resolution that best matches the display device.
FIG. 7
is a flowchart illustrating the sequence of processing performed in a microcomputer which performs resolution conversion at an analog interface. The illustrated example assumes the case where an image is displayed on an SXGA (Super XGA) LCD panel designed for a resolution of 1280×1024 pixels. As shown in the flowchart, the microcomputer first measures the period of the input horizontal sync signal (HS) and computes its frequency f from that period.
If f<40 kHz, it is determined that the input display mode is VGA mode (640×480 pixels), and the pixel density scaling factor is set to two. If 40 kHz≦f<50 kHz, it is determined that the input display mode is SVGA (Super VGA) mode (800×600 pixels), and the pixel density scaling factor is set to 1.6. If 50 kHz≦f<60 kHz, it is determined that the input display mode is XGA mode (1024×768 pixels), and the pixel density scaling factor is set to 1.25. Further, if 60 kHz≦f, it is determined that the input display mode is the intended SXGA mode (1280×1024 pixels), and the pixel density scaling factor is set to unity.
The frequencies used as thresholds in the above processing are only illustrative. VGA alone uses a variety of horizontal sync frequencies and, since a large amount of resources is required if the resolution is to be identified by only using hardware, a microcomputer must be used as described above. However, it is difficult to accurately identify the frequency of the sync signal by using a microcomputer, and there arises the possibility that optimum resolution conversion may not be achieved. Furthermore, not only is it required to provide a microcomputer as an external device, but the firmware for it has to be developed.
SUMMARY OF THE INVENTION
In view of the above problems and the recent trend toward digital interfaces for video signals, it is an object of the present invention is to provide a method and apparatus for converting a digital video signal to a signal having a resolution that matches a display device by only using simple hardware and by eliminating the need to develop firmware.
In the present invention, a digital video signal interface handles a data enable signal and a dot clock signal in addition to the horizontal and vertical sync signals as handled by prior art analog interfaces and, to achieve the above object, the invention employs the technical configuration described hereinafter by noting that there exists a predefined relationship between the data enable and dot clock signals.
More specifically, according to the present invention, there is provided a method for converting the resolution of a digital video signal that is input together with a data enable signal and a dot clock signal, comprising the steps of: counting the number of clocks of the dot clock signal generated during an active period of the data enable signal; identifying the resolution of the input video signal based on the number of clocks thus counted; and converting, based on the identified resolution, the pixel density of the input video signal so as to form a video signal having a resolution that matches a display device.
According to the present invention, there is also provided a method for converting the resolution of a digital video signal that is input together with a data enable signal and a dot clock signal, comprising the steps of: counting the number of pulses of the data enable signal generated during one vertical synchronization period; identifying the resolution of the input video signal based on the number of pulses thus counted; and converting, based on the identified resolution, the pixel density of the input video signal so as to form a video signal having a resolution that matches a display device.
The method of the present invention further comprises the step of identifying the one vertical synchronization period based on the number of clocks of the dot clock signal generated during an inactive period of the data enable signal.
According to the present invention, there is also provided an apparatus for converting the resolution of a digital video signal that is input together with a data enable signal and a dot clock signal, comprising: count means for counting the number of clocks of the dot clock signal generated during an active period of the data enable signal; identifying means for identifying the resolution of the input video signal based on the number of clocks counted by the count means; and pixel density converting means for converting, based on the resolution identified by the identifying means, the pixel density of the input video signal so as to form a video signal having a resolution that matches a display device.
According to the present invention, there is also provided an apparatus for converting the resolution of a digital video signal that is input together with a data enable signal and a dot clock signal, comprising: count means for counting the number of pulses of the data enable signal generated during one vertical synchronization period; identifying means for identifying the resolution of the input video signal based on the number of pulses counted by the count means; and pixel density converting means for converting, based on the resolution identified by the identifying means, the pixel density of the input video signal so as to form a video signal having a resolution that matches a display device.
The apparatus of the present invention further comprises means for identifying the one vertical synchronization period based on the number of clocks of the dot clock signal generated during an inactive period of
Fujitsu Limited
Mengistu Amare
Nguyen Jimmy H.
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