Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
2002-06-13
2008-11-04
Huisman, David J (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S207000, C712S225000, C712S226000
Reexamination Certificate
active
07447877
ABSTRACT:
A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an instruction pipeline when the current thread is switched out may be decoded and then converted to the complementary prefetch operations. The prefetch operation may place the data into the cache during the execution of the alternate thread.
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patent: 6073215 (2000-06-01), Snyder
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Intel® Itanium™ Architecture Software Developer's Manual, vol. 3: Instruction Set Reference Revision 2.0, Dec. 2001, 3 pages.
Pudipeddi Bharadwaj
Walterscheidt Udo
Huisman David J
Intel Corporation
Trop Pruner & Hu P.C.
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