Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Reexamination Certificate
2002-11-20
2004-09-28
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
C331S017000, C331S025000, C327S156000
Reexamination Certificate
active
06798297
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly, but not exclusively, to control loops.
2. Description of the Background Art
Electrical circuits with control loops are well known in the art. In digital clock circuits, for example, a digital control loop may be employed to synchronize an output clock with an incoming reference signal. Such digital clock circuits may be used for clock recovery, clock generation, and other timing-related applications.
A conventional digital control loop
100
is schematically illustrated in FIG.
1
. In control loop
100
, RefIn
110
is an input reference signal to a digital phase detector
101
. Phase detector
101
also receives FBIn
112
, which is a feedback signal presented by a digitally controlled oscillator (DCO)
105
. FBIn
112
or another output signal of DCO
105
may be used to provide timing information to other circuits not specifically shown. For example, FBIn
112
may be used as a synchronizing clock.
Phase detector
101
presents a phase error signal, referred to as “RefLead
114
”, based on a phase difference between RefIn
110
and FBIn
112
. RefLead
114
may be a 1-bit digital signal that is in a logical HIGH state when RefIn
110
is leading FBIn
112
in phase, and in a logical LOW state when RefIn
110
is lagging FBIn
112
in phase. A loop filter comprising a pre-count divider
102
and an up/down counter
103
helps stabilize the loop. Pre-count divider
102
receives RefLead
114
and, depending on the number of RefLeads
114
going in a particular direction it has received, presents an up signal or a down signal to up/down counter
103
. Up/down counter
103
increments its count upon receipt of an up signal, and decrements its count upon receipt of a down signal.
Still referring to
FIG. 1
, an adder
104
adds RefLead
114
to the output of the count of up/down counter
103
. The resulting sum from adder
104
, referred to as “DCOIn
116
”, is presented as a control signal to DCO
105
. DCO
105
adjusts the frequency of FBIn
112
according to DCOIn
116
. The process of receiving RefIn
110
, determining if RefIn
110
is leading or lagging FBIn
112
, and accordingly controlling DCO
105
to adjust the frequency of FBIn
112
is repeated for several cycles until FBIn
112
and RefIn
110
have the same phase and frequency.
Like most digital phase detectors, phase detector
101
is of the so-called “bang-bang” type. Specifically, unlike its analog counterpart, phase detector
101
can only tell if RefIn
110
is leading or lagging FBIn
112
—phase detector
101
cannot tell the amount of phase mismatch between the two signals. Thus, in control loop
100
, the amount of phase mismatch between a reference signal and a feedback signal is ignored in converging the loop. Instead, the frequency of the feedback signal is continually adjusted until the feedback signal and the reference signal are in phase and have the same frequency. One problem with this approach is that it may take a lot of cycles before the loop converges.
SUMMARY
In one embodiment, a control loop in an electrical circuit includes a variable feed-forward circuit configured to determine a setting of a variable oscillator that would result in a frequency of a first signal approximating a frequency of a second signal. The setting may be used to control the variable oscillator at a time when a phase error between the first signal and the second signal is negligibly small (e.g., substantially zero), thus allowing for relatively short loop convergence time.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.
REFERENCES:
patent: 5168245 (1992-12-01), Koskowich
Kwan King H.
Stansell Galen E.
Cypress Semiconductor Corporation
Mis David
Okamoto & Benedicto LLP
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