Patent
1994-04-06
1997-06-24
Donaghue, Larry D.
395591, 395800, G06F 1516, G06F 938, G06F 1128
Patent
active
056424990
ABSTRACT:
In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.
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MC 68020 32-Bit Microprocessor User's Manual; 1985 Section 8.
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"The MC68881 Floating-point Coprocessor" 1983, Huntsman et al.
Kida Hiroyuki
Morinaga Shigeki
Ohba Mamoru
Watabe Mitsuru
Donaghue Larry D.
Hitachi , Ltd.
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