Method and apparatus for controlling the output voltage provided

Details Method and apparatus for controlling the output voltage provided Method and apparatus for controlling the output voltage provided

1996-06-19

1996-09-03

Zarabian, A.

Static information storage and retrieval

Powering

36518533, G11C 700

Patent

active

055530303

ABSTRACT:
An integrated circuit arrangement for providing operating voltages for a flash EEPROM memory array, which integrated circuit arrangement utilizes a plurality of charge pumps in a staggered output arrangement to generate a high voltage output while generating lower amounts of current from each individual charge pump so that the provision of the necessary current is integrated over the entire period of the voltage output. Unique circuitry is provided for regulating the value of the output voltage produced by the arrangement in response to variations in the output voltage produced.

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1992 IEEE International Solid-State Circuits Conference, ISSCC 92 Session 9/Non-Volatile and Dynamic RAMS/Paper 9.3, "TP9.3: A 5V-Only 0.6 .mu.m Flash EEPROM with ROW Decoder Scheme in Triple-Well Structure," Masao Kurlyama, et al., pp. 152-153, 270.

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