Static information storage and retrieval – Floating gate – Particular biasing
Patent
1993-09-10
1995-08-15
Clawson, Jr., Joseph E.
Static information storage and retrieval
Floating gate
Particular biasing
36518909, 365218, 365226, 365900, G11C 1606
Patent
active
054425867
ABSTRACT:
An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.
REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5153854 (1992-10-01), Herold
patent: 5157278 (1992-10-01), Min et al.
patent: 5216588 (1993-06-01), Bajwa et al.
patent: 5243561 (1993-09-01), Yamauchi
patent: 5245572 (1993-09-01), Kosonocky et al.
patent: 5267196 (1993-11-01), Talreja et al.
patent: 5267218 (1993-11-01), Elbert
patent: 5276646 (1994-01-01), Kim et al.
patent: 5280447 (1994-01-01), Hazen et al.
patent: 5287317 (1994-02-01), Kobayashi et al.
patent: 5297096 (1994-03-01), Terada et al.
patent: 5313429 (1994-05-01), Chevallier et al.
patent: 5315547 (1994-05-01), Shoji et al.
patent: 5317535 (1994-05-01), Talreja et al.
patent: 5327384 (1994-07-01), Ninomiya
patent: 5329488 (1994-07-01), Hashimoto
patent: 5337281 (1994-08-01), Kobayashi et al.
patent: 5339279 (1994-08-01), Toms et al.
patent: 5375094 (1994-12-01), Naruke
1992 IEEE International Solid-State Circuits Conference, ISSCC 92 Session 9/Non-Volatile and Dynamic RAMS/Paper 9.3, "TP9.3: A 5V-Only 0.6.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure," Masao Kurlyama, et al., pp. 152-153, 270.
Brennan, Jr. James
Fazio Albert
Javanifard Jahanshir J.
Larsen Robert E.
Tedrow Kerry D.
Clawson Jr. Joseph E.
Intel Corporation
LandOfFree
Method and apparatus for controlling the output current provided does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for controlling the output current provided, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for controlling the output current provided will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2187908