Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-03-14
1995-10-03
Clawson, Jr., Joseph E.
Static information storage and retrieval
Floating gate
Particular biasing
365226, 36523006, G11C 1606
Patent
active
054557941
ABSTRACT:
An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.
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"TP9.3: A 5V-Only 0.6 .mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", pp. 152-153 and 170, by Masao Kuriyama, Shigeru Alsumi, Axira Umezawa, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Sejii Yamada, Etsushi Obi.
Masamitsu Oshikiri, Tomoko Suzuki, Mashashi Wada, Sumio Tanaka, 1992 IEEE International Solid-State Circuits Conference, ISSCC92 Session 9/Non-Volatile and Dynamic RAMS/Paper 9.3.
Brennan, Jr. James
Fazio Albert
Javanifard Jahanshir J.
Larsen Robert E.
Tedrow Kerry D.
Clawson Jr. Joseph E.
Intel Corporation
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