Method and apparatus for controlling read and write...

Details Method and apparatus for controlling read and write... Method and apparatus for controlling read and write...

1998-06-19

2002-07-23

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S032000

Reexamination Certificate

active

06424476

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a disk drive apparatus for a hard disk drive (HDDs), and more particularly to a disk drive apparatus including a head assembly having a plurality of heads for performing recording/regeneration on a storage medium which is wire mounted on a printed circuit board.
2. Description of Related Art
As the industry demands further miniaturization of hard disk drives (HDDs), which are used to provide external storage for an information processor, there is a need to reduce the number of wires between the head assembly and the printed-circuit board.
A conventional technique of this kind is described, for example, in IBM Technical Disclosure Bulletin, vol. 39, No. 7, July 1996, pp. 175-176.
FIG. 13
is a block diagram illustrating an interface circuit of a conventional HDD
10
. The HDD
10
includes a hard disk controller (HDC)
11
for controlling an operation of reading or writing data from or to a magnetic disk, a microprocessing unit (MPU)
12
for controlling the entire operation of HDD
10
, a preamplifier
13
for performing reading/writing of data on a magnetic head, and a channel module
14
for controlling preamplifier
13
by various control signals. The HDC
11
and the MPU
12
are referred to as digital systems.
The channel module
14
includes a waveform shaping circuit, a phase-locked loop (PLL) circuit, a frequency synthesizer circuit, and an encoder/decoder. The channel module
14
converts digital data signals from a user to data write signals and also converts analog signals from preamplifier
13
to digital signals.
The channel module
14
is controlled by a read gate control signal, a write gate control signal, a servo gate control signal, a servo data control signal, an in-channel register control signal, and the other control signals. These signals are transmitted over corresponding signal lines connected in parallel. Also, control signals for preamplifier
13
, which includes some of the aforementioned control signals, are directly connected and controlled, through noise reduction circuits such as a filter and a buffer by a digital system. In addition, channel module
14
transmits data read/write signals between the digital systems and the channel module over a data bus using a few bits.
The following signals provide input to or output from preamplifier
13
over corresponding signal lines: head select signals HSEL
0
, HSEL
1
, and HSEL
2
; current write signals WCURR
0
and WCURR
1
; a head control signal MRBIAS; a preamplifier-fault write signal AEWFAULT; a preamplifier characteristic control signal TA; a write gate signal WGT; and a power save read/write signal RWPS. The signals WGT and RWPS are input to channel module
14
over corresponding signal lines. Also, the preamplifier
13
and channel module
14
are coupled by data write signal lines WDT+ and WDT− and analog-data read signal lines RDX and RDY.
In addition, MPU
12
and channel module
14
are coupled by a serial register control signal line SENA, a serial clock signal SCLK line, and a serial data signal SDT line.
A data and servo switching signal SRVAREA, an AGC hold signal AGCHOLD, a clear signal CLEAR, a burst detection timing specifying signal BURSTW, a POR reset signal POR, a read gate signal RGT, and a clock signal OSC are transmitted from HDC
11
to channel module
14
over corresponding signal lines. Additionally, a servo data signal SRVDT, a reference clock read signal RRCLK, a serial clock signal SRVSC, and a serial data signal SRVSD are transmitted from the channel module
14
to HDC
11
over corresponding signal lines. User data read/write signals NRZ
0
, NRZ
1
, NRZ
2
, NRZ
3
provide bidirectional signals between the HDC
11
and the channel module
14
.
However, the interface circuit described above has several drawbacks. For Example, HDC
11
and MPU
12
may not have a sufficient number of pins for all the control signals between HDC
11
and MPU
12
. Particularly, as future generations of disk drives increase the number of the signals NRZ
0
through NRZ
3
(for example, from 4 signals to 8 signals), the number of pins is insufficient.
An additional drawback is that the direct coupling of HDC
11
, MPU
12
, channel module
14
and preamplifier
13
(which is sensitive to noise) causes a high error rate which requires that filters be inserted or buffers having a common power supply must be interposed.
Furthermore, as data rates increase in HDDS, it is difficult to write data to the disk if the inductance of the head wire is too large at the preamplifier. For this reason, the preamplifier is mounted near the heads, and consequently, the distance between the preamplifier and the channels on a card causes the preamplifier to be influenced by noise. Because there are a great number of control signals, channels cannot be mounted on a flexible cable near to the preamplifier.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a disk drive which is capable of reducing the number of control signals for performing reading and writing operations.
A disk drive apparatus of the present invention including a head, an amplifier, a control unit, and a channel is described. The head is operable to read or write data from or to a storage medium. The amplifier is operable to amplify data for the head. The control unit is operable to control the operation of reading out servo information for reading or writing data from or to the head. The channel is operable to convert a digital data signal to a data write signal and also to convert an analog signal from the amplifier to a digital signal. The channel is controlled by the control unit. The control of the channel by the control unit is performed over a bus which is also used to transmit or receive a data read/write signal.
For one embodiment of the present invention, when the channel is performing data communication, the control information is not transmitted. For an alternative embodiment of the present invention, the control information transmitted over the bus is read out at predetermined bus-cycle intervals in correspondence with requested control. For other embodiments of the present invention, the channel generates a control signal to control the amplifier in response to the control information.
A circuit used in a storage device is also described. The circuit includes an amplifier operable to amplify a data read signal from a storage medium or a data write signal to the storage medium. The circuit also includes a control unit for controlling reading or writing data operations. The channel is coupled to the amplifier via a data signal line. The channel is operable to convert between an analog signal and a digital signal. The control unit controls the operation of reading or writing data from or to the storage medium, by controlling a signal on the data signal line.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description below.


REFERENCES:
patent: 5233482 (1993-08-01), Galbraith et al.
patent: 5321559 (1994-06-01), Nguyen et al.
patent: 5726821 (1998-03-01), Cloke et al.
patent: 5829011 (1998-10-01), Glover
patent: 5918068 (1999-06-01), Shafe
patent: 8-77576 (1996-03-01), None
patent: 08083403 (1996-03-01), None
patent: 8-293176 (1996-11-01), None
patent: 8-315529 (1996-11-01), None
patent: 9-147508 (1997-06-01), None

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