Oscillators – Combined with particular output coupling network
Reexamination Certificate
2001-06-11
2004-09-28
Pascal, Robert (Department: 2817)
Oscillators
Combined with particular output coupling network
C331S1160FE, C331S1170FE, C331S109000, C331S158000, C331S183000
Reexamination Certificate
active
06798301
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to crystal oscillators. More particularly, the present invention relates to oscillation amplitude control and oscillation frequency control of crystal oscillators.
BACKGROUND OF THE INVENTION
Crystal oscillators are used in many applications to provide an accurate and stable frequency reference such as a clock signal. In most cases it is also required to be able to pull the crystal around the center frequency so that the oscillator can be enclosed in a timing loop. Although the amplitude of oscillation is often not a system requirement, for a number of reasons it is still important to have a well defined amplitude of oscillation. For example, since the power dissipated in a crystal depends on the amplitude of oscillation, the oscillation amplitude cannot exceed several milliwatts in order to ensure stable crystal frequency with aging. Furthermore, in many applications, electrostatic discharge (ESD) protection devices are connected to the pads in a chip to which the crystal oscillator is coupled. Uncontrolled oscillation amplitude may cause overshoots and undershoots, and the ESD protection devices will be turned on when the voltage goes below ground voltage. This will cause clipping in the waveform and introduce jitter in the output clock signal. In addition, a stable amplitude can also lead to a more robust design of a buffer following the crystal oscillator that converts the oscillation voltage to standard COMS logic levels.
One of the best known oscillator structures is the so-called three-point oscillator.
FIG. 1A
schematically illustrates the basic structure of a three-point oscillator
1
. Depending on which of the three points is an AC ground (nodes
2
,
3
, or
4
), the circuit is referred to as a Pierce, Colpitts, or Clapp oscillator. As shown in
FIG. 1A
, the crystal oscillator
1
includes a crystal resonator
5
, a transistor
6
(M
1
), a first capacitor
7
(C
1
), and a second capacitor
8
(C
2
). It is well known that the Pierce configuration has, among these three configurations, some of the best properties with respect to frequency stability. In
FIG. 1A
, the crystal resonator
5
which is coupled between the node
2
and
3
is illustrated as an equivalent circuit of L
s
, C
s
, and R
5
. A capacitance C
0
is a crystal static capacitance referred to as the “shunt” capacitance and includes a capacitance due to the electrodes on the crystal plate and stray capacitance due to the crystal enclosure.
It is well known that transistor M
1
(with a transconductance g
m
) combined with capacitors C
1
and C
2
constitutes a frequency dependent negative resistance (−R) in series with C
1
and C
2
, as shown in FIG.
1
B. The negative resistance is given as:
-
R
=
g
m
ω
0
C
1
C
2
.
(
1
)
When the capacitance of capacitors C
1
and C
2
are much higher than the shunt capacitance C
0
, as are in practical designs, Equation (1) can be used to estimate the critical transconductance g
mc
of the transistor M
1
as:
g
mc
=R
s
&ohgr;
0
2
C
1
C
2
(2).
The critical transconductance g
mc
is the minimum transconductance required to compensate the loss due to the motional resistance R
s
of the crystal resonator
5
and sustain the oscillation. For the best trade-off between frequency stability and required transconductance, the capacitors C
1
and C
2
should be equal.
FIG. 2
illustrates a basic circuit structure of a conventional Pierce oscillator
10
. As shown in
FIG. 2
, the conventional Pierce oscillator
10
includes a crystal resonator
12
, a current source
14
supplying a bias current to the crystal resonator
12
, and an output transistor
16
(M
1
) coupled to the crystal resonator
12
and the current source
14
. The crystal resonator
12
may be externally coupled to the chip on which the oscillator circuitry is implemented, as the connection is indicated by a broken line. A transistor
18
coupled between the output and input nodes of the crystal resonator
12
provides a bias resistance Rbias, the gate of which is couple to a bias voltage V
b1
. Capacitors
15
and
17
(C
1
and C
2
) are also coupled to the crystal resonator
12
. The two capacitors
15
and
17
are typically identical switched-capacitor arrays and used to tune the oscillation frequency. The tuning range and resolution depend on the tolerance of CMOS device values, stray (parasitic) capacitances of the capacitor arrays, and the maximum trimming capacitance.
As is seen from
FIG. 2
, when most of the noise up to the current source
14
is filtered, the primary noise contributors are the current source
14
, the transistor
16
, and the bias transistor
18
(neglecting the loss in the crystal and other noise injection through the voltage supply and substrate). The design task mainly consists of minimizing noise from these components whilst making sure that oscillations can be sustained at all times. The bias current required by the oscillator
10
depends on the amplitude of oscillation, the losses in the crystal, and also other process and environment parameters. Thus, a fixed bias circuit may not be able to guarantee oscillations over all conditions, nor find an optimum value to minimize power and ensure a fixed oscillation.
Accordingly, it would be desirable to provide a scheme to control an oscillation amplitude at an optimal level so as to increases the noise immunity of the crystal oscillator and at the same time to keep the amplitude small enough to avoid waveform distortion such as clipping by ESD protection devices. In addition, it would be desirable to provide a scheme of digitally tuning the oscillation frequency around a center frequency with an appropriate range and resolution required for applications.
BRIEF DESCRIPTION OF THE INVENTION
A circuit controls an oscillation amplitude of a crystal oscillator, the crystal oscillator including a crystal resonator, a current source supplying a bias current to the crystal resonator, and an output transistor coupled to the crystal resonator and the current source. The circuit includes a peak detector coupled to an output of the crystal oscillator for detecting a peak voltage of an output signal of the crystal oscillator, and a controller coupled to the peak detector and to the current source for controlling the current source in accordance with a difference between the peak voltage and a target voltage, the target voltage being set to be substantially equal to 2V
th
, where V
th
is a threshold voltage of the output transistor. The crystal oscillator further includes a first capacitor array coupled between the input node and a second supply voltage, and a second capacitor array coupled between the output node and the second supply voltage. The first capacitor array includes a first plurality of switched-capacitors, and the second capacitor array includes a second plurality of switched-capacitors. A frequency control circuit is coupled to the first capacitor array and the second capacitor array. The frequency control circuit includes an input for receiving a frequency control signal, and a capacitance controller for alternately switching a switched-capacitor in the first capacitor array and a switched-capacitor in the second capacitor array for successive changes in capacitance based on the frequency control signal.
REFERENCES:
patent: 5030926 (1991-07-01), Walden
patent: 5349309 (1994-09-01), Fujii
patent: 6278338 (2001-08-01), Jansson
patent: 6559730 (2003-05-01), Marvin et al.
Huang et al., “Design Considerations for High-Frequency Crystal Oscillators Digitally Trimmable to Sup-ppm Accuracy”, Dec. 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, No. 4, pp 408-416.
Balan Vishnu
Pan Tzu-Wang
Glenn Kimberly
LSI Logic Corporation
Pascal Robert
Thelen Reid & Priest LLP
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