Method and apparatus for controlling noise on power supply buses

Details Method and apparatus for controlling noise on power supply buses Method and apparatus for controlling noise on power supply buses

1990-11-23

1991-10-22

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307440, H03K 1716, H03K 19003

Patent

active

050598228

ABSTRACT:
A method and apparatus for controlling ground bounce and transient noise induced in an integrated circuits power supply buses by feeding back the input/output power supply bus voltages levels and comparing those levels to the internal logic power supply bus voltage levels. Significant noise transients on the input/output upper potential power supply bus will increase a resistance of a series element in each buffer circuit that drives a respective output driver and thereby increase the overall switching time of each buffer and output driver combination. Similarly, significant ground bounce voltages on the input/output lower potential power supply bus will increase a resistance of another series element in each buffer circuit driving its respective output driver and thereby increase the overall switching time of each buffer and output driver combination. Increasing the switching time is known to reduce noise transients caused by switching currents, but by only increasing the switching time when the noise transients caused by switching currents reach a troublesome level, the remainder data switching of the output driver may be provided at a higher data rate.

REFERENCES:
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4825099 (1989-04-01), Barton
patent: 4906866 (1990-03-01), Alexander et al.
"A 25-ns 4-Mbit CMOS SRAM with Dynamic Bit-Line Loads" by Fumio Miyaji, et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1213-1218.

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