Method and apparatus for controlling (N+I) I/O channels with (N)

Details Method and apparatus for controlling (N+I) I/O channels with (N) Method and apparatus for controlling (N+I) I/O channels with (N)

1996-12-31

1999-01-26

Shin, Christopher B.

395855, 395845, 395873, G06F 1310

Patent

active

058647120

ABSTRACT:
A method an corresponding apparatus for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to interleave contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a first I/O channel with contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a second I/O channel, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled by the single data manager based on the availability of data from the I/O devices' buffer memories, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager. The apparatus and methods of the present invention are also extended to encompass a plurality "n" of data managers interleaving contiguous block transfers among a larger plurality "n+i" of I/O devices.

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