Multiplex communications – Data flow congestion prevention or control
Reexamination Certificate
2006-03-14
2006-03-14
Duong, Frank (Department: 2666)
Multiplex communications
Data flow congestion prevention or control
C370S232000, C370S253000, C370S413000
Reexamination Certificate
active
07012889
ABSTRACT:
Methods and apparatuses are disclosed for controlling the rate at which packets are sent from a first to a second component of a packet switching system. In one implementation, the first component represents an input line card to a packet switch, and the second component represents an output of the packet switch. In such a system, a state is maintained for each output at each line card. For example, these states may include an unconstrained state during which traffic is sent at a full rate to the output, an off state during which no traffic is sent to the output, and a constrained state during which traffic is sent at a reduced rate to the output. Typically, this reduced rate is proportional to the arrival rate of packets at the input line card which are destined for the output. The state of the output is changed based on received flow control information about the output and whether traffic remains queued for the output at the input line card.
REFERENCES:
patent: 4491945 (1985-01-01), Turner
patent: 4494230 (1985-01-01), Turner
patent: 4630259 (1986-12-01), Larson et al.
patent: 4630260 (1986-12-01), Toy et al.
patent: 4734907 (1988-03-01), Turner
patent: 4745593 (1988-05-01), Stewart
patent: 4829227 (1989-05-01), Turner
patent: 4849968 (1989-07-01), Turner
patent: 4893304 (1990-01-01), Giacopelli et al.
patent: 4901309 (1990-02-01), Turner
patent: 5027342 (1991-06-01), Boulton et al.
patent: 5127000 (1992-06-01), Henrion
patent: 5161156 (1992-11-01), Baum et al.
patent: 5173897 (1992-12-01), Schrodi et al.
patent: 5179551 (1993-01-01), Turner
patent: 5179556 (1993-01-01), Turner
patent: 5229990 (1993-07-01), Teraslinna
patent: 5229991 (1993-07-01), Turner
patent: 5253251 (1993-10-01), Aramaki
patent: 5260935 (1993-11-01), Turner
patent: 5265092 (1993-11-01), Soloway et al.
patent: 5339311 (1994-08-01), Turner
patent: 5402415 (1995-03-01), Turner
patent: 5471460 (1995-11-01), Tanabe
patent: 5475682 (1995-12-01), Choudhury et al.
patent: 5533020 (1996-07-01), Byrn et al.
patent: 5689500 (1997-11-01), Chiussi et al.
patent: 5768572 (1998-06-01), George et al.
patent: 5842040 (1998-11-01), Hughes et al.
patent: 5844890 (1998-12-01), Delp et al.
patent: 5848227 (1998-12-01), Sheu
patent: 6246665 (2001-06-01), Watanabe et al.
patent: 6337851 (2002-01-01), Charny et al.
patent: 6343067 (2002-01-01), Drottar et al.
patent: 6366557 (2002-04-01), Hunter
patent: 6411599 (2002-06-01), Blanc et al.
patent: 6418115 (2002-07-01), Iino et al.
patent: 6424624 (2002-07-01), Galand et al.
patent: 6430150 (2002-08-01), Azuma et al.
patent: 6526060 (2003-02-01), Hughes et al.
patent: 6654342 (2003-11-01), Dittia et al.
patent: 6674721 (2004-01-01), Dittia et al.
patent: 6674726 (2004-01-01), Kado et al.
patent: 6728211 (2004-04-01), Peris et al.
patent: 6735173 (2004-05-01), Lenoski et al.
patent: 6747972 (2004-06-01), Lenoski et al.
patent: 6788689 (2004-09-01), Turner et al.
patent: 6816492 (2004-11-01), Turner et al.
patent: 6826186 (2004-11-01), Dittia et al.
Zubin Dittia, “Integrated Hardware/Software Design of a High Performance Network Interface,” Mar. 2000, Doctor of Science Thesis, Sever Institute of Technology, Washington University, St. Louis, Missouri, 139 pages.
Jonathan S. Turner, “An Optimal Nonblocking Multicast Virtual Circuit Switch,” Jun. 1994, Proceedings of Infocom, 8 pages.
Chaney et al., “Design of a Gigabit ATM Switch,” Feb. 5, 1996, WUCS-96-07, Washington Univeristy, St. Louis, MO, 20 pages.
Turner et al., “System Architecture Document for Gigabit Switching Technology,” Aug. 27, 1998, Ver. 3.5, ARL-94-11, Washington University, St. Louis, MO, 110 pages.
U.S. Appl. No. 09/519,282, filed Mar. 7, 2000, Lenoski et al.
U.S. Appl. No. 09/705,395, filed Nov. 2, 2000, Turner et al.
George Varghese and Anthony Lauck, “Hashed and Hierarchical Timing Wheels: Efficient Data Structures for Implementing a Timer Facility,” IEEE/ACM Transactions on Networking, vol. 5, No. 6, Dec. 1997, pp. 824-834.
Dittia Zubin D.
Turner Jonathan S.
Cisco Technology Inc.
Duong Frank
Scheibel, Jr. Robert C.
The Law Office of Kirk D. Williams
LandOfFree
Method and apparatus for controlling input rates within a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for controlling input rates within a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for controlling input rates within a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3588675