Method and apparatus for controlling I/O channels responsive to

Details Method and apparatus for controlling I/O channels responsive to Method and apparatus for controlling I/O channels responsive to

1996-08-26

1999-04-13

Shin, Christopher B.

395827, 395840, G06F 1300

Patent

active

058945601

ABSTRACT:
An apparatus and method for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to chain contiguous DMA scatter gather sub blocks of a PRD table for channel 0 with contiguous DMA scatter gather sub blocks of a PRD table for channel 1, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled based on the availability of data from the I/O device's buffer memory, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.

REFERENCES:
patent: 4371932 (1983-02-01), Dinwiddie, Jr. et al.
patent: 4782439 (1988-11-01), Borkar et al.
patent: 4805137 (1989-02-01), Grant et al.
patent: 4807121 (1989-02-01), Halford
patent: 4821170 (1989-04-01), Bernick et al.
patent: 4831523 (1989-05-01), Lewis et al.
patent: 5016160 (1991-05-01), Lambeth et al.
patent: 5031097 (1991-07-01), Katakami et al.
patent: 5131081 (1992-07-01), MacKenna et al.
patent: 5179709 (1993-01-01), Bailey et al.
patent: 5185876 (1993-02-01), Nguyen et al.
patent: 5206933 (1993-04-01), Farrell et al.
patent: 5212795 (1993-05-01), Hendry
patent: 5251303 (1993-10-01), Fogg, Jr. et al.
patent: 5251312 (1993-10-01), Sodos
patent: 5301279 (1994-04-01), Riley et al.
patent: 5305319 (1994-04-01), Sowell
patent: 5355476 (1994-10-01), Fukumura
patent: 5367639 (1994-11-01), Sodos
patent: 5386532 (1995-01-01), Sodos
patent: 5388219 (1995-02-01), Chan et al.
patent: 5388237 (1995-02-01), Sodos
patent: 5404454 (1995-04-01), Parks
patent: 5418909 (1995-05-01), Jackowski et al.
patent: 5438665 (1995-08-01), Taniai et al.
patent: 5551006 (1996-08-01), Kulkarni
patent: 5574944 (1996-11-01), Stager
patent: 5613162 (1997-03-01), Kabenjian
patent: 5655151 (1997-08-01), Bowes et al.
patent: 5671439 (1997-09-01), Klein et al.
patent: 5687392 (1997-11-01), Radko
patent: 5701516 (1997-12-01), Cheng et al.
patent: 5740466 (1998-04-01), Goldman et al.
IBM Technical Disclosure Bulletin, Jan., 1994; DMA Controller Channel Interlocking; vol. 37, No. 1; pp. 337-342.
IBM Technical Disclosure Bulletin, Feb., 1995; Priority Scheme for Arithemetic Logic Unit and Dataflow Usage by P1394 Isochronous Hardware; vol. 38, No. 2; pp. 477-480.
Programming Interface for Bus Master IDE Controller Revision 0.9; Jun. 14, 1994; Brad Hosler; Intel Corporation; pp. 1-6.

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