Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-08-09
2002-07-16
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185330
Reexamination Certificate
active
06421276
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the operation of a non-volatile memory system. More specifically, the present invention relates to an improved method and apparatus for enabling a system user to control erase operations in a non-volatile memory system.
BACKGROUND OF THE INVENTION
Non-volatile memory cells are typically arranged in discrete arrays or blocks. During an erase operation, all of the non-volatile memory cells in a block are erased simultaneously. Over-erase conditions may exist in certain memory cells if the erase operation is carried out for too long. In order to prevent over-erase, an erase operation is typically performed with a number of short erase pulses.
FIG. 1
is a flow chart illustrating a conventional erase operation for a block of a non-volatile memory system. The erase operation is initiated in response to an ERASE command. Upon starting the erase operation (Step
101
), an initial erase verify address is selected (Step
102
). This initial erase verify address typically corresponds with the first address of the block being erased. An erase pulse is applied in parallel to all of the memory cells in the block (Step
103
).
After the erase pulse has been applied, all memory cells in the block must be verified as having been erased before the erase operation is concluded (Step
104
). The erase verify operation is initialized by an ERASE VERIFY command. The erase verify operation starts at the initial erase verify address and sequentially proceeds to the subsequent addresses in the block until a non-erased memory cell is found, or until the last address of the block is accessed. More specifically, if a non-erased memory cell is detected during the erase verify operation, processing returns to Step
103
, and another erase pulse is applied. Erase verification then resumes at Step
104
, beginning at address at which the non-erased memory cell was previously detected.
If an erased memory cell is detected during the erase verify operation, then it is determined whether the current erase verify address is equal to the last address in the block. (Step
105
). If not, then the current erase verify address is incremented (Step
106
), and processing returns to Step
104
for another erase verify operation.
If an erased memory cell is found during the erase verify operation, and the current erase verify address corresponds with the last address of the block, then all of the memory cells have been verified as having been erased. At this time, the erase operation is complete (Step
107
).
In some non-volatile memory systems, different portions of the non-volatile memory array are coupled to receive separate erase pulses. Two examples of such systems are described below.
In a first non-volatile memory system, the erase pulse can only be applied to a subset of a non-volatile memory array at any one time, due to power limitations. In this case, the memory array is typically divided into a plurality of equal-sized blocks. Erase operations are then performed separately for each block, with erase pulses being applied in turn to each block.
In a second non-volatile memory system, each of the non-volatile memory cells stores 2-bits of information. As defined herein, each of these 2-bit non-volatile memory cells stores a right (R) bit and a left (L) bit. U.S. Pat. No. 5,768,192 to Eitan describes one such non-volatile memory cell.
FIG. 2
is a schematic diagram illustrating a 3×3 array
200
of 2-bit non-volatile memory cells M
0,0
-M
2,2
, each having a right bit (R) and a left bit (L). In array
200
, each column of memory cells has a dedicated pair of bit lines. In array
200
(which is typically much larger than 3×3), an erase operation is performed in two steps. In one step, a first erase pulse is applied to the even bit lines BL
0
, BL
2
and BL
4
, thereby erasing the right bits (R) of memory cells M
0,0
-M
2,2
. In the other step, a second erase pulse is applied to the odd bit lines BL
1
, BL
3
and BL
5
, thereby erasing the left bits (L) of memory cells M
0,0
-M
2,2
. The combined duration of the first and second erase pulses is significantly less than the required duration of a single erase pulse that erases all of the even and odd bits in parallel.
FIG. 3
is a schematic diagram illustrating a 3×3 array
300
of 2-bit non-volatile memory cells M
0,0
-M
2,2
, each having a right bit (R) and a left bit (L). In array
300
, bit lines are shared by adjacent columns of memory cells. In array
300
(which is typically much larger than 3×3), an erase operation is performed in two steps. In one step, a first erase pulse is applied to the even bit lines BL
0
and BL
2
, thereby erasing the right bits (R) of the memory cells in the first column, the left bits (L) of the memory cells in the second column, and the right bits (R) of the memory cells in the third column. In the other step, a second erase pulse is applied to the odd bit lines BL
1
and BL
3
, thereby erasing the left bits (L) of the memory cells in the first column, the right bits (R) of the memory cells in the second column, and the left bits (L) of the memory cells in the third column. Again, the combined duration of the first and second erase pulses is significantly less than the required duration of a single erase pulse that erases all of the even and odd bits in parallel. Array
300
, as well as the circuitry used to access array
300
, is described in U.S. Pat. No. 6,081,456 to Dadashev.
In different applications, the erase operation can be controlled externally by the system user or by internal circuitry of the non-volatile memory system. The memory control circuit of a non-volatile memory system is significantly simpler when erase operations are controlled externally by the system user. However, in the above-described arrays, the system user must select which blocks or bit lines receive the various erase pulses. Consequently, the standard erase method illustrated by the flowchart of
FIG. 1
cannot be utilized, and new commands must be added to the standard command set. The new commands must enable the selection of even/odd bit lines and/or particular memory blocks to be erased.
It would therefore be desirable to have a method and apparatus for erasing non-volatile memory systems having 2-bit memory transistors and/or multiple blocks, wherein the method and apparatus are compatible with the standard erase operation defined by the flowchart of FIG.
1
.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an interface for automatically selecting the part of the non-volatile memory system to be erased by the next erase pulse. The invention advantageously enables a system user to implement the conventional erase method illustrated by the flowchart of FIG.
1
.
In one embodiment, the non-volatile memory system includes an array of 2-bit non-volatile memory cells having a set of odd bit lines and a set of even bit lines. A user command interface is provided to receive an ERASE command from a system user. In response, the user command interface asserts an ERASE signal.
An erase bit pointer is coupled to receive the ERASE signal from the user command interface. The erase bit pointer is configured to generate an ODD_EVEN control signal that toggles between a first state and a second state in response to a predetermined edge of the ERASE signal.
Erase logic is coupled to receive the ERASE signal and the ODD_EVEN control signal. The erase logic is configured to apply an ERASE pulse to the set of odd bit lines when the ODD_EVEN control signal has the first state and the ERASE signal is asserted. The erase logic is further configured to apply an ERASE pulse to the set of even bit lines when the ODD_EVEN control signal has the second state and the ERASE signal is asserted.
After each ERASE pulse has timed out, the system user asserts an ERASE VERIFY command. In response, the user command interface asserts a VERIFY control signal and an erase verify address. These signals are provided to read logic. In response, read logic reads a data value from the era
Bever Hoffman & Harms LLP
Hoffman E. Eric
Phan Trong
Tower Semiconductor Ltd.
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