Method and apparatus for controlling data transfers between a bu

Details Method and apparatus for controlling data transfers between a bu Method and apparatus for controlling data transfers between a bu

1995-09-29

1998-09-22

Sheikh, Ayaz R.

395427, G06F 1338, G06F 1200

Patent

active

058128034

ABSTRACT:
A method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller includes a memory controller having a data controller unit and a data path unit. Signals are passed between the data controller unit and the data path unit, thereby providing an interface between the two units. The data controller receives control signals from the bus and provides commands to the data path unit in response to these control signals. The commands provided to the data path unit enable the data path unit to transfer data to and from the bus and memory device.

REFERENCES:
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patent: 5526506 (1996-06-01), Hyatt
Gwennap, Linley, "Intel's P6 bus designed for multiprocessing . . . ", Microprocessor Report, v9, n7, pp. 1-6, May 30, 1995.
Uffenbeck, John, "The 8086/8088 Family: Design, Programming, and Interfacing", Regents/Prentice Hall, New Jersey, pp. 327-330, 1987.
Popescu, Val, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-31 and 63-73.

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