Method and apparatus for controlling data output frequency

Coded data generation or conversion – Digital code to digital code converters – With error detection or correction

Reexamination Certificate

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C326S041000

Reexamination Certificate

active

06879272

ABSTRACT:
Broadly speaking, a method and corresponding apparatus is provided for controlling a data output rate of an electronic device. More specifically, the method and corresponding apparatus enables an equivalent data output rate to be obtained from each of an ASIC and an FPGA prototype of the ASIC while maintaining equivalent logic between the ASIC and the FPGA prototype. A validity bit is attached to each output data signal in accordance with each cycle of a clock signal. The validity bit provides an indication as to whether the associated data signal should be processed (i.e., transmitted as output) normally. Only valid output data signals as identified by their validity bit value are transmitted. Thus, the validity bit values associated with successive data signals can be defined to generate a particular data output rate.

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patent: 6690193 (2004-02-01), Heinzer et al.

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