Method and apparatus for controlling clock skew in an integrated

Details Method and apparatus for controlling clock skew in an integrated Method and apparatus for controlling clock skew in an integrated

1997-06-30

1998-10-27

Heckler, Thomas M.

395552, G06F 112

Patent

active

058288708

ABSTRACT:
A method for controlling clock skew in an integrated circuit which includes a plurality of functional blocks which each contain a control circuit that is in communication with a gated clock includes: a) providing a source clock signal to the control circuit, b) providing a reference clock signal to the control circuit, the reference clock signal being substantially derived from the source clock signal, wherein the reference clock signal has a reference clock phase delay that is greater a phase delay of the gated clock, c) generating a control signal using the reference clock signal and the gated clock, the control signal being arranged to indicate a relationship between the reference clock signal and the gated clock, and d) generating a controlled gated clock using the control signal, wherein the controlled gated clock is generated at least in part by adding a suitable delay to the source clock signal, the controlled gated clock having a controlled gated clock phase delay which is substantially the same as the reference clock phase delay. In some embodiments, the reference clock signal and the source clock signal are provided by a frequency synthesizer.

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