Method and apparatus for controlling clock signals

Details Method and apparatus for controlling clock signals Method and apparatus for controlling clock signals

1998-06-15

2000-07-25

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327119, H03B 1900

Patent

active

06094076&

ABSTRACT:
A clock signal control circuit includes a divider dividing an external clock signal into multiple phase clock signals, timing difference dividers connected to the divider for dividing a difference in phase of pulses between the multiple phase clock signals having different phases from each other to generate different phase clock signals, a single multiplexer connected to the timing difference dividers for multiplexing the different phase clock signals to generate multiplexed clock signals, and a synthesizer connected to the multiplexers for synthesizing the multiplexed clock signals into a single multiplied clock signal.

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T. Shimizu et al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM", pp. 216-217, IEEE International Solid-State Circuits Conference, Feb. 9, 1996.
Chih-King Ken Yang et al., "A 0.8 .mu.m CMOS 2.5GB/s Oversampled Receiver for Serial Links", pp. 200-201, IEEE International Solid-State Circuits Conference, 1996.
M. Combes, et al., "A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells", pp. 958-965, IEEE Journal of Solid-State Circuits, vol. 31, No. 1, Jul. 1996.

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