Method and apparatus for controlling clock signal period

Details Method and apparatus for controlling clock signal period Method and apparatus for controlling clock signal period

1997-08-18

1999-02-23

Heckler, Thomas M.

G06F 108

Patent

active

058753214

ABSTRACT:
In a clock signal generating apparatus, an internal clock signal generating circuit generates an internal clock signal. An adjustment data storing section stores an adjusted period designating data and an adjustment content designating data. In this case, the adjusted period designating data indicates ones of N periods (N is an integer larger than 1) of a desired clock signal for adjustment to be performed to obtain the desired clock signal, and adjustment content designating data indicates a content of the adjustment. One period of the desired clock signal is composed of a plurality of periods of the internal clock signal. An adjustment requesting section selectively issues an adjustment request based on the adjusted period designating data and the adjustment content designating data in response to input of desired clock signal. A desired clock signal generating section performs the adjustment in response to the adjustment request while counting pulses of the internal clock signal. As a result, each of specific periods of the N periods designated by the adjusted period designating data is extended or shortened by at least one period of the internal clock signal based on adjustment content designating data. Then, the desired clock signal generating section generates desired clock signal based on the adjustment result.

REFERENCES:
patent: 5146601 (1992-09-01), Hosaka et al.
patent: 5461266 (1995-10-01), Koreeda et al.
"Variable Duration Microprocessor Clock Generation", pp. 116-123, IBM Technical Disclosure Bulletin, vol. 31, Nov. 12, May 1989.

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