Method and apparatus for controlling access to memory which is c

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39520008, 395287, 36493446, 36493701, 36496427, 364DIG2, G06F 1300

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055308384

ABSTRACT:
There is provided a common-memory controlling apparatus which controls data transfer between a common-memory and a plurality of central processing units. A separating buffer separates a CPU bus connected to each of the central processing units from a common-memory bus connected to the common-memory. A request signal generating circuit generates a request signal for accessing to the common-memory when each of the central processing units requires accesses to the common-memory. An arbitration circuit arbitrates the request signals supplied by the central processing units so that a request signal corresponding to one of the central processing units is selected. The central processing unit having the highest priority level is served. A control signal generating unit generates control signals used for controlling a bus connection corresponding to the selected central processing unit so that the CPU bus connected to the selected central processing unit is connected to the common-memory.

REFERENCES:
patent: 4257095 (1981-03-01), Nadir
patent: 4395753 (1983-07-01), Comfort et al.
patent: 4633392 (1986-12-01), Vincent et al.
patent: 4837682 (1989-06-01), Culler
patent: 4924380 (1990-05-01), McKinney et al.

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