Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-10-18
2005-10-18
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S015000
Reexamination Certificate
active
06957318
ABSTRACT:
A method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree of the graph, propagating a first command from the host computer to a member of the processor array using the broadcast tree, configuring a reply tree from a spanning tree of the graph, transmitting a response from the member of the processor array to the host computer using the reply tree, and configuring the data connection component to send at least one message selected from the first command and the response on at least one run mode communication path.
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Broughton Jeffrey M.
Burr James B.
Emberson David R.
Pappas Derek E.
Coleman Eric
Osha & Liang LLP
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