Patent
1994-06-08
1996-07-09
Black, Thomas G.
395800, G06F 714, G06F 716
Patent
active
055353843
ABSTRACT:
A method and apparatus for controlling a hardware merge sorter to sort N.gtoreq.2.sup.n number of records, the hardware merge sorter including a plurality of local processors that are cascaded in series, a plurality of local memories and a plurality of selectors. Each selector is coupled to and between one of the plurality of local memories and a respective local processor and couples the local memory to the respective processor during a first sorting step. In addition, the plurality of local memories are coupled to one local processor, of the plurality of local processors, during a second sorting step. With this arrangement, the hardware merge sorter can sort a plurality N.ltoreq.2.sup.n+1 number of records. In one particular embodiment of the present invention, a plurality of hardware merge sorter cells are cascaded in series. With this arrangement, the hardware merge sorter can sort a plurality N.ltoreq.2.sup.n+2 number of records.
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K. E. Batcher "Sorting Networks and their Applications" AFIPS Conference Proceedings vol. 32, pp. 307-314, 1968.
Black Thomas G.
Mitsubishi Denki & Kabushiki Kaisha
Wang Peter Y.
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