Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Patent
1996-03-08
1997-08-05
Auve, Glenn A.
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
345838, 345868, 345734, G06F 126
Patent
active
056551274
ABSTRACT:
A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.
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Bhatt Ajay V.
Bogin Zohar
Kardach James P.
Rabe Jeffrey L.
Shah Nilesh V.
Auve Glenn A.
Intel Corporation
Seto Jeffrey K.
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