Method and apparatus for constructing verification test sequence

Details Method and apparatus for constructing verification test sequence Method and apparatus for constructing verification test sequence

1995-03-06

1998-08-18

Beausoliel, Jr., Robert W.

Excavating

364488, G06F 1100

Patent

active

057967520

ABSTRACT:
Verification Test Sequences (43) (VTS) are constructed for use in testing conformance of a Machine-Under-Test (14) (MUT) with a Finite State Machine (33) (FSM) model.
The number of incoming and outgoing Test Subsequence (TS) graph (39) micro-edges are determined for each TS graph (39) vertex or Finite State Machine (33) state. An Augmented Graph (95) is created (40) by constructing Test Subsequence (TS) micro-edge bridging sequences between TS graph vertices with relatively more incoming micro-edges and vertices with relatively more outgoing micro-edges. The newly symmetric Augmented Graph (95) is Euler Toured (42), generating Verification Test Sequences (43), used to test a Machine-Under-Test (14) for conformance with the FSM model (33).

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